Exploring Branch Predictors for Constructing Transient Execution Trojans

Zhang, Tao; Koltermann, Kenneth; Evtyushkin, Dmitry

doi:10.1145/3373376.3378526

Cited by 22 publications

(28 citation statements)

References 38 publications

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“…The baseline reflects the branch predictor (including structure sizes) used in Intel Skylake microarchitecture. Derived based on recent reverseengineering works [16], [18], [33], [36], [46], [85], it represents a generalization of mechanisms used in modern Intel processors. STBPU can be applied to different branch predictors, e.g., [68], [69], as it adds security guarantees without altering any prediction principles.…”

Section: B Bpu Baseline Modelmentioning

confidence: 99%

“…Mode two is only used when predicting indirect branches, and serves as a fall-back mechanism for predicting returns. This addressing enables storing multiple targets for a single indirect branch depending on the context [16], [33], [85]. PHT is a large (16k entry) table consisting of n-bit (e.g.…”

Section: B Bpu Baseline Modelmentioning

confidence: 99%

“…This structure is used as a base predictor to predict the direction of conditional branches. Previous studies [7], [18], [25], [85] indicated presence of mechanism similar to gshare [83] with two modes of addressing: the simple 1-level mode where virtual address of branch is used to find a PHT entry, and a more complex 2-level mode where the branch virtual address is hashed with global history register (GHR) enabling accurate prediction complex patterns. RSB is used to predict return instructions.…”

Section: B Bpu Baseline Modelmentioning

confidence: 99%

“…If branch predictor is flushed on context switch attacks such as Spectre v2, Jump-over-ASLR and others can be fully mitigated. Soure and target branch addresses and calls, taken/nontaken patterns [3], [16], [18], [36], [39] Timing channel due to A controlling predictions in V [3], speculative execution attacks [13], [33], [36], [46], [67], [85] V's jmp taken/nontaken [3] and call pattens, branch instruction virtual address [33] Timing channel due to A forcing static default predictions [3], speculatively execute gadget at static prediction address [ Intel has proposed a set of microcode-based protections which aim to mitigate speculative execution attacks on legacy CPUs by restricting BPU structure sharing. These protections include Indirect Branch Restricted Speculation (IBRS), Indirect Branch Prediction Barrier (IBPB), and Single Threaded Indirect Branch Prediction (STIBP) [27].…”

Section: Existing Protections Against Bpu Attacksmentioning

confidence: 99%

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STBPU: A Reasonably Secure Branch Prediction Unit

Zhang¹,

Lesch²,

Koltermann³

et al. 2021

Preprint

Self Cite

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Modern processors have suffered a deluge of dangerous side channel and speculative execution attacks that exploit vulnerabilities rooted in branch predictor units (BPU). Many such attacks exploit the shared use of the BPU between unrelated processes, which allows malicious processes to retrieve sensitive data or enable speculative execution attacks. Attacks that exploit collisions between different branch instructions inside the BPU are among the most dangerous. Various protections and mitigations are proposed such as CPU microcode updates, secured cache designs, fencing mechanisms, invisible speculations. While some effectively mitigate speculative execution attacks, they overlook BPU as an attack vector, leaving BPU prone to malicious collisions and resulting critical penalty such as advanced micro-op cache attacks. Furthermore, some mitigations severely hamper the accuracy of the BPU resulting in increased CPU performance overhead. To address these, we present the secret token branch predictor unit (STBPU), a branch predictor design that mitigates collision-based speculative execution attacks and BPU side channel whilst incurring little to no performance overhead. STBPU achieves this by customizing inside data representations for each software entity requiring isolation. To prevent more advanced attacks, STBPU monitors hardware events and preemptively changes how STBPU data is stored and interpreted.

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Section: B Bpu Baseline Modelmentioning

confidence: 99%

Section: B Bpu Baseline Modelmentioning

confidence: 99%

Section: B Bpu Baseline Modelmentioning

confidence: 99%

Section: Existing Protections Against Bpu Attacksmentioning

confidence: 99%

See 2 more Smart Citations

STBPU: A Reasonably Secure Branch Prediction Unit

Zhang¹,

Lesch²,

Koltermann³

et al. 2021

Preprint

Self Cite

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show abstract

“…With the prevalence of public cloud computing, the operating system can be compromised in some hostile environments, which makes security attacks even easier. Branch predictors are one of the earliest discovered and frequently targeted side-channels [8,9,21,22,50]. They can be vulnerable because different contexts 1 share them within the same physical core.…”

Section: Introductionmentioning

confidence: 99%

Securing Branch Predictors with Two-Level Encryption

Lee

Ishíi

Sunwoo

2020

ACM Trans. Archit. Code Optim.

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Modern processors rely on various speculative mechanisms to meet performance demand. Branch predictors are one of the most important micro-architecture components to deliver performance. However, they have been under heavy scrutiny because of recent side-channel attacks. Branch predictors are indexed using the PC and recent branch histories. An adversary can manipulate these parameters to access and control the same branch predictor entry that a victim uses. Recent Spectre attacks exploit this to set up speculative-executionbased security attacks. In this article, we aim to mitigate branch predictor side-channels using two-level encryption. At the first level, we randomize the set-index by encrypting the PC using a per-context secret key. At the second level, we encrypt the data in each branch predictor entry. While periodic key changes make the branch predictor more secure, performance degradation can be significant. To alleviate performance degradation, we propose a practical set update mechanism that also considers parallelism in multi-banked branch predictors. We show that our mechanism exhibits only 1.0% and 0.2% performance degradation while changing keys every 10K and 50K cycles, respectively, which is much lower than other state-of-the-art approaches. CCS Concepts: • Security and privacy → Side-channel analysis and countermeasures; • Computer systems organization → Architectures;

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