Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC

Oliveira, Ádria Barros de; Tambara, Lucas Antunes; Kastensmidt, Fernanda Lima

doi:10.1007/978-3-319-56258-2_17

Cited by 12 publications

(4 citation statements)

References 12 publications

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“…SP, LR, PC) located in the register files of the ARM cores. The fault injection strategy adopted in our work is the same as in [17], i.e. the interrupt mechanism is used to be minimally intrusive.…”

Section: Fault Injection Techniquementioning

confidence: 99%

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Kasap

Wächter

Zhai

et al. 2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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An attractive option for realizing applications in radiation environments is to employ All-Programmable Systemon-Chips (APSoCs) thanks to their high-performance computing and power efficiency merits. Despite APSoC's advantages, like any other electronic device, they are prone to radiation effects. Processors found in APSoCs must, therefore, be adequately hardened against ionizing-radiation to become a viable alternative for harsh environments. This paper proposes a novel triple-core lockstep (TCLS) approach to secure the Xilinx Zynq-7000 APSoC dual-core ARM Cortex-A9 processor against radiation-induced soft errors by coupling it with a MicroBlaze TMR subsystem in Zynq's programmable logic (PL) layer. The proposed strategy uses software-level checkpointing principles along with roll-back and roll-forward mechanisms (i.e. software redundancy), and hardware-level processor replication as well as checker circuits (i.e. hardware redundancy). Results of fault injection experiments show that the proposed solution achieved high soft error security by mitigating about 99% of bit-flips injected into both ARM cores' register data.

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Section: Fault Injection Techniquementioning

confidence: 99%

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Kasap

Wächter

Zhai

et al. 2020

2020 IEEE Nordic Circuits and Systems Conference (NorCAS)

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“…The USB-TTL Converter, responsible for transmitting the serial data, is connected to the ZedBoard and the host computer. The adopted methodology follows the same scheme presented in [18]. The system consists of the following modules:…”

Section: Fault Injection and Error Classificationmentioning

confidence: 99%

ARFT: An Approximative Redundant Technique for Fault Tolerance

Rodrigues¹,

Oliveira²,

Bosio³

et al. 2018

2018 Conference on Design of Circuits and Integrated Systems (DCIS)

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This paper presents a novel redundancy technique for software fault tolerance, named Approximative Redundant Fault Tolerance (ARFT). It uses approximate computing in order to provide the same error detection of a classic DWC method with less overhead. In this work ARFT was implemented to protect the ARM Cortex-A9 embedded into Zynq-7000 All Programmable SoC. An extensive fault injection campaign was performed to evaluate the proposed technique. Results show that distinct applications with different approximation methods present a big variation in terms of execution time, memory footprint and error detection capability. Performance analysis shows that ARFT can reduce the overhead in some benchmarks cases up to 40%.

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“…Hence, the functionality of any system implemented into an APSoC can be partitioned between PL and PS while the PS can also take the control over the PL. Among the APSoC devices, the Xilinx Zynq-7000 fabricated in the Taiwan Semiconductor Manufacturing Company's 28 nm technology node has been vastly used for different applications in recent years [6]- [8]. Routing resources in Xilinx APSoC fabrics are controlled by SRAM cells that are called configuration bits [9].…”

Section: Introductionmentioning

confidence: 99%

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics

Darvishi¹

2020

Preprint

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This paper presents an automated algorithm for optimum configuration of routing interconnection network in Xilinx Zynq-7000 All programmable system-on-chip (APSoC) fabrics. A method to configure circuits with optimum routing resources is presented along with their performance parameters with and without the proposed algorithm. The proposed algorithm enables full control over routing resources for using different interconnection types in order to create routing-based circuit-undertest. The algorithm proposes the routing techniques through the 2-D array of switch matrices inside the interconnection network and automatically identifies the involved programmable interconnection points associated with a node. An experimental setup is proposed to measure the performance parameters such as slack time and power with and without the applied algorithm on the APSoC routing resources. The proposed setup requires no external equipment such as manufactured equipments or external instruments for performance measurement.

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Exploring Performance Overhead Versus Soft Error Detection in Lockstep Dual-Core ARM Cortex-A9 Processor Embedded into Xilinx Zynq APSoC

Cited by 12 publications

References 12 publications

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

Novel Lockstep-based Approach with Roll-back and Roll-forward Recovery to Mitigate Radiation-Induced Soft Errors

ARFT: An Approximative Redundant Technique for Fault Tolerance

Optimum Reconfiguration of Routing Interconnection Network in APSoC Fabrics

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