Exploring performance tradeoffs for clustered VLIW ASIPs

Jacome, Margarida F.; Veciana, Gustavo de; Lapinskii, V.

doi:10.1109/iccad.2000.896523

Cited by 12 publications

(11 citation statements)

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“…A data routing approach in [26] tries to find better ways to transfer data among datapath components to reduce interconnect complexity. A distributed VLIW architecture is discussed in [17], and applications are mapped onto this architecture by fully exploring the temporal and spacial locality of both computations and communi- cations. These approaches focus on scheduling techniques, while none of them focus on the resource binding stage.…”

Section: (A)mentioning

confidence: 99%

Platform-based resource binding using a distributed register-file microarchitecture

Cong¹,

Fan²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

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Section: (A)mentioning

confidence: 99%

Platform-based resource binding using a distributed register-file microarchitecture

Cong¹,

Fan²

2006

Proceedings of the 2006 IEEE/ACM International Conference on Computer-Aided Design - ICCAD '06

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“…Jacome et. al in [10] proposed a design space exploration method for VLIW ASIP datapaths. In [13], Kathail et al proposed a design flow named PICO (Program In Chip Out) for a specific SoC (System-on-Chip) design, where parallelism exploration is tackled at different design levels including at the instruction level with VLIWs.…”

Section: Related Workmentioning

confidence: 99%

Customization of application specific heterogeneous multi-pipeline processors

Radhakrishnan

Guo

Parameswaran

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…Along with finding the appropriate abstractions, the challenge is to identify the critical dimensions of the design space, i.e., those capturing the salient performance/cost tradeoffs, and to develop complementary algorithms for design space exploration. As will be discussed shortly, this goal is achieved by using a suitable parameterization of the design space of clustered VLIW datapaths [15].…”

mentioning

confidence: 99%

Application-specific clustered VLIW datapaths: early exploration on a parameterized design space

Lapinskii

Jacome

Veciana

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level parallelism inherent in many embedded media applications, while unlocking a variety of possible performance/cost tradeoffs. In this work, the authors propose a methodology to support early design space exploration of clustered VLIW datapaths, in the context of a specific target application. They argue that, due to the large size and complexity of the design space, the early design space exploration phase should consider only design space parameters that have a first-order impact on two key physical figures of merit: clock rate and power dissipation. These parameters were found to be: maximum cluster capacity, number of clusters, and bus (interconnect) capacity. Experimental validation of their design space exploration algorithm shows that a thorough exploration of the complex design space can be performed very efficiently in this abstract parameterized design space. Moreover, an empirical study carried out on a representative set of computation-intensive benchmarks suggests that "penalties" of clustered versus centralized datapaths are often minimal and that clustering indeed unlocks a variety of valuable design tradeoffs.

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Exploring performance tradeoffs for clustered VLIW ASIPs

Cited by 12 publications

References 10 publications

Platform-based resource binding using a distributed register-file microarchitecture

Platform-based resource binding using a distributed register-file microarchitecture

Customization of application specific heterogeneous multi-pipeline processors

Application-specific clustered VLIW datapaths: early exploration on a parameterized design space

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