Exploring the Design Space of Power-Aware Opto-Electronic Networked Systems

Abstract

As microprocessors become increasingly interconnected, the power consumed by the interconnection network can no longer be ignored. Moreover, with demand for link bandwidth increasing, optical links are replacing electrical links in inter-chassis and inter-board environments. As a result, the power dissipation of optical links is becoming as critical as their speed. In this paper, we first explore options for building high speed opto-electronic links and discuss the power characteristics of different link components. Then, we propose circuit and network mechanisms that can realize power-aware optical links -links whose power consumption can be tuned dynamically in response to changes in network traffic. Finally, we incorporate power-control policies along with the power characterization of link circuitry into a detailed network simulator to evaluate the performance cost and power savings of building power-aware opto-electronic networked systems. Simulation results show that more than 75% savings in power consumption can be achieved with the proposed power-aware opto-electronic network.