Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor-Transistor Hybrid FPGA Architecture

Aslam, M. Hassan; Farooq, Umer; Awais, Muhammad Naeem; Bhatti, Muhammad Khurram; Shehzad, Naeem

doi:10.1007/s13369-016-2068-8

Cited by 9 publications

(3 citation statements)

References 29 publications

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“…First, data flow control is quite crude (the flow is either there or it is not). The delay in the execution of commands can lead to unjustified idle of the transmitter and the periodic occurrence of new overloads, in which some of the packets [5], including those belonging to other flows, will be lost [6].…”

Section: This Methods Has Several Drawbacksmentioning

confidence: 99%

Controlling Data Flows in Computer Networks

Aa¹

2018

Preprint

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In computer networks, loss of data packets is inevitable, in particular, because of the buffer memory overflow of at least one of the nodes located on the path from the source to the receiver, including the latter. Such losses associated with overflows are hereinafter referred to as congestion of network nodes. There are many ways to prevent and eliminate overloads; these methods, in the majority, are based on the management of data flows. A special place is taken by the maintenance of packages, taking into account their priorities. The article considers a number of original technical solutions to improve the quality of control and reduce the required amount of buffer memory of network nodes. The ideas of these solutions are quite simple for their implementation in the development of appropriate software and hardware for telecommunication devices.

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Section: This Methods Has Several Drawbacksmentioning

confidence: 99%

Controlling Data Flows in Computer Networks

Aa¹

2018

Preprint

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“…Figure 1: I-V characteristics of fundamental circuit elements [14] Memristor defines the reationship between magnetic flux and electric flux through the following equation:…”

Section: Generic Voltage-controlled Memristor Modelmentioning

confidence: 99%

An Advanced 1-bit Arithmetic Logic Unit (ALU) with Hybrid Memristor-CMOS Architecture

Azmine¹,

Debnath²,

Arafat³

2021

Preprint

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<div>Memristor is dubbed as the fourth fundamental electrical component which works primarily as a non-volatile memory element. Memristors can also be used to construct logic gates, and Memristor Ratioed Logic (MRL) is one of these structures. The higher area efficiency and CMOS architecture compatibility of MRL gates have lead researchers to pay attention to its use in digital logic architecture. In this work, binary MRL is integrated with Complementary Metal-Oxide Semiconductor(CMOS) logic elements to develop building blocks of an Arithmetic Logic Unit (ALU). The proposed 1-bit ALU is simulated using LTSpice, which allows the versatility of changing the parameters as per the model used. This work designs and analyses an optimized cascadable 1-bit ALU with with voltage level based binary logic state via simulation. The proposed circuit shows improvement in transistor count and delay over benchmark circuits.</div>

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“…[17][18][19] As an important class of organic materials, coordination polymers demonstrate attractive switching properties and exhibit promising applications in the data storage eld. [20][21][22] Compared with polymers that have pure organic skeletons, coordination polymers comprising metal and organic ligands offer a potential alternative due to their facile preparation and high thermal stability, combining the advantages of both polymers and metal complexes. Particularly, by the exible design of metal and organic constituents as well as by modifying the functional groups in the coordination complexes, the properties of memory devices based on the resultant coordination polymers can be ne-tuned.…”

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confidence: 99%