Exploring the Limitations of Software-based Techniques in SEE Fault Coverage

Processors are main part of the calculation and decision making of a system. Today, due to the increasing need of industry and technology to faster and more accurate computing power, design and manufacture of parallel processing units, has been very much considered. One of the most important processor families used in various devises is the MIPS processors. This processor family had been considered in the telecom and control industry as a reasonable choice. In this paper, new architecture based on this processor, with new parallel processing design, is provided to allow parallel execution of instructions dynamically. Ultimately, the processor efficiency to several fold will be increased. In this architecture, new ideas for the issuance of instructions in parallel, intelligent detection of conditional jumps and memory management are presented.

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“…But the number of ports of writing will be two. The reason for this constraint is a steady increase in register file [3,4].…”

Section: -4-multiple Issue Architecturementioning

confidence: 99%

Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

Hadizadeh

Tanghatari

2018

ESJ

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“…In addition, they introduce significant performance penalties. These limitations are particularly relevant in the case of control-flow error mitigation [4].…”

Section: Introductionmentioning

confidence: 99%

PTM-based hybrid error-detection architecture for ARM microprocessors

Pena-Fernandez

Lindoso

Entrena

et al. 2018

Microelectronics Reliability

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This work presents a hybrid error detection architecture that uses ARM PTM trace interface to observe ARM microprocessor behaviour. The proposed approach is suitable for COTS microprocessors because it does not modify the microprocessor architecture and is able to detect errors thanks to the reuse of its trace subsystem. Validation has been performed by proton irradiation and fault injection campaigns on a Zynq AP SoC including a Cortex-A9 ARM microprocessor and an implementation of the proposed hardware monitor in programmable logic. Experimental results demonstrate that a high error detection rate can be achieved on a commercial microprocessor.

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“…In recent years, a large number of techniques based on redundant software, also known as Software Implemented Hardware Fault Tolerance (SIHFT) techniques [3], have been proposed as a cost-effective alternative to traditional approaches based on hardware. Although SIHFT can be easily applied to COTS processors, they * Corresponding author cause non-negligible overheads in terms of code size, execution time, and data storage [4]. These overheads present a challenge for designing fault tolerant systems and, in any case, they impose new limitations to their reliability.…”

Section: Introductionmentioning

confidence: 99%

SHARC: An efficient metric for selective protection of software against soft errors

Isaza-Gonzalez

Restrepo-Calle

Martínez-Álvarez

et al. 2018

Microelectronics Reliability

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This paper presents a metric for the efficient application of selective hardening using software based techniques against soft-errors. It offers a method for selecting the resources to be protected obtaining maximum fault coverage with the minimum overhead. Common approaches are based on exhaustive exploration of the solution space or time-consuming fault injection campaigns. Contrarily, our Software based HARdening Criticality metric (SHARC) relies on early estimations of the impact that protection techniques will have on the global reliability of the application. SHARC estimations are based on features extracted from the dynamic analysis of source code, and produce a prioritization of the resources involved accordingly. For assessing our approach two case studies were carried out using low-cost embedded microprocessors. Results were compared to traditional approaches like brute-force exploration and the Architectural Vulnerability Factor (AVF) metric. Experiments show that SHARC improves the results between 5% and 21% at a fraction of the effort.

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Exploring the Limitations of Software-based Techniques in SEE Fault Coverage

Cited by 18 publications

References 14 publications

Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

Parallel Processor Architecture with a New Algorithm for Simultaneous Processing of MIPS-Based Series Instructions

PTM-based hybrid error-detection architecture for ARM microprocessors

SHARC: An efficient metric for selective protection of software against soft errors

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