Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units

Bhagyanath, Anoop; Schneider, Klaus

doi:10.1109/acsd.2017.20

“…As shown in and (Bhagyanath and Schneider 2017), it is sufficient that the order of two variables V 1 ,V 2 produced by a PU PU is preserved in their operands V 1,L/R and V 2,L/R , if both operands are produced by the same PU PU 2 .…”

Section: Var(x) : − Operand(xy Z) Var(y ) : − Operand(xy Z) Varmentioning

confidence: 99%

“…Similar to the SMT encoding (Bhagyanath and Schneider 2017), an assignment of variables to timeslots is used in this encoding. However, this approach did not scale well as the number of constraints grows enormously with the number of variables.…”

Section: Optimal Scheduling Regarding Execution Timementioning

confidence: 99%

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Dahlem¹,

Bhagyanath²,

Schneider³

2018

EasyChair Preprints

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Conventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the relatively low number of programmer-visible registers. Therefore, more recent processor architectures expose their datapaths so that the compiler (1) can schedule parallel instructions to different processing units and (2) can make effective use of local storage of the processing units. Among these architectures, the Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture whose processing units are equipped with first-in first-out (FIFO) buffers at their input and output ports.In contrast to register-based machines, the optimal code generation for SCAD is still a matter of research. In particular, SAT and SMT solvers were used to generate optimal resource constrained and optimal time constrained schedules for SCAD, respectively. As Answer Set Programming (ASP) offers better flexibility in handling such scheduling problems, we focus in this paper on using an answer set solver for both resource and time constrained optimal SCAD code generation. As a major benefit of using ASP, we are able to generate all optimal schedules for a given program which allows one to study their properties. Furthermore, the experimental results of this paper demonstrate that the answer set solver can compete with SAT solvers and outperforms SMT solvers. This paper is under consideration for acceptance in TPLP.

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“…Repeated invocation of the SAT solver by incrementing the number of PUs allowed one to determine the minimal number of PUs required to execute programs without any computational overhead. Since execution time is a more important metric in instruction scheduling, we refined the SAT encoding in (Bhagyanath and Schneider 2017) to a satisfiability modulo theories (SMT) problem, introducing execution time as an additional parameter for optimization. The non-linearity of buffer constraints (a property specific to SCAD as discussed in Section 3) did not allow the use of integer linear programming solvers that is more commonly used in instruction scheduling.…”

Section: Motivationmentioning

confidence: 99%

“…The SAT encoding in was then used to determine the minimal number of PUs required in a SCAD machine to execute a given basic block without any overhead. This was refined to an SMT encoding in (Bhagyanath and Schneider 2017) to determine the minimal execution time of a given basic block on a SCAD machine with a given number of PUs (greater than or equal to the minimal number required for overhead free execution).…”

Section: Code Generation For Scadmentioning

confidence: 99%

“…Our test part demands the order to fulfill additional constraints to allow the variable productions in a way that the computations of the basic block still can be performed. As shown in and (Bhagyanath and Schneider 2017), it is sufficient that the order of two variables V 1 ,V 2 produced by a PU PU is preserved in their operands V 1,L/R and V 2,L/R , if both operands are produced by the same PU PU 2 .…”

Section: Var(x) : − Operand(xy Z) Var(y ) : − Operand(xy Z) Varmentioning

confidence: 99%

See 1 more Smart Citation

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Dahlem

¹

,

Bhagyanath

²

,

Schneider

³

2018

Theory and Practice of Logic Programming

Self Cite

2

0

View full text Add to dashboard Cite

Conventional processor architectures are restricted in exploiting instruction level parallelism (ILP) due to the relatively low number of programmer-visible registers. Therefore, more recent processor architectures expose their datapaths so that the compiler (1) can schedule parallel instructions to different processing units and (2) can make effective use of local storage of the processing units. Among these architectures, the Synchronous Control Asynchronous Dataflow (SCAD) architecture is a new exposed datapath architecture whose processing units are equipped with first-in first-out (FIFO) buffers at their input and output ports.In contrast to register-based machines, the optimal code generation for SCAD is still a matter of research. In particular, SAT and SMT solvers were used to generate optimal resource constrained and optimal time constrained schedules for SCAD, respectively. As Answer Set Programming (ASP) offers better flexibility in handling such scheduling problems, we focus in this paper on using an answer set solver for both resource and time constrained optimal SCAD code generation. As a major benefit of using ASP, we are able to generate all optimal schedules for a given program which allows one to study their properties. Furthermore, the experimental results of this paper demonstrate that the answer set solver can compete with SAT solvers and outperforms SMT solvers. This paper is under consideration for acceptance in TPLP.

show abstract

A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units

Anders

¹

,

Schneider

²

2019

2019 19th International Conference on Application of Concurrency to System Design (ACSD)

0

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Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units

Cited by 10 publications

References 18 publications

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

A Formal Semantics of Exposed Datapath Architectures with Buffered Processing Units

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