Expression of Concern: On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

This paper presents a pre-layout inductance modeling approach for on-chip interconnect in the high-speed digital design context. Regarding the impact of the inductance on delays, assumptions on the current return path localization are compared. The influence of neighboring signal lines on the effective inductance is highlighted. Particularly, their inclusion in inductance models when the clock frequency increases is discussed. Finally, representative structure models allowing pre-layout effective inductance corner estimations are presented.

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Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

Mondal¹,

Massoud²

2005

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

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The increasing demand for high performance ICs and system on chip necessitates reliable methodologies for reducing pessimism in chip design. In this paper, we investigate how the frequency dependence of loop self inductance affects the RLC delay. We show that the pessimism in the estimation of RLC propagation delay could be as high as 30% if the frequency dependence of inductance is not considered properly. As a means of efficiently computing less pessimistic RLC delay values, we present an analytical model of frequency dependent loop self inductance that can be applied to model a wide range of real design scenarios. We demonstrate that our approach is computationally efficient and produces accurate and realistic (less pessimistic) delay values that lead to significantly improved system performance.

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Expression of Concern: On the accuracy of return path assumption for loop inductance extraction for 0.1 μm technology and beyond

Abstract: The most common assumption for chip-level

Cited by 37 publications

References 9 publications

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line

Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line

Models for pre-layout inductance estimation including frequency effects on current return path in advanced digital circuits

Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

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