Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

Mondal, M.; Massoud, Yehia

doi:10.1109/iccad.2005.1560154

Cited by 60 publications

(30 citation statements)

References 20 publications

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“…New methods must be identified so that unachievable or hard to achieve constraints can be relaxed to manageable levels. Efforts in [1] and [2] target crosstalk noise and RLC delay pessimism reduction respectively. One such method is necessary for interconnect matching.…”

Section: Introductionmentioning

confidence: 99%

Generation of design guarantees for interconnect matching

Kahng

Topaloglu

2006

Proceedings of the 2006 International Workshop on System-Level Interconnect Prediction

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Manufacturable design requires matching of interconnects which have equal nominal dimensions. New design rules are projected to bring guarantee rules for interconnect matching. In this paper, we present a methodology to generate additional guarantees given the limited set of guarantees in the design manual. In order to achieve this, we propose a multi-function optimization method to extract parameters of a preliminary dimension-and distance-based process correlation model for interconnects. We propose an interconnect matching extraction method and suitable patterns useful for mismatch extraction. We have extracted matching guarantees while also considering the special case of edge matching using Monte Carlo analysis and field solvers. We have substantiated the experimentation with evaluations on a preliminary regression model and metric for mismatch.

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Section: Introductionmentioning

confidence: 99%

Generation of design guarantees for interconnect matching

Kahng

Topaloglu

2006

Proceedings of the 2006 International Workshop on System-Level Interconnect Prediction

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“…Aggressive feature scaling and increasing operating frequencies greatly impact the performance of high speed integrated circuits [1]. As the complexity of on-chip systems increases, the accurate and efficient modeling of interconnect is vital for estimating and controlling delay, cross-talk noise, and power consumption [2].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Multi-Point Rational Interpolation for Frequency-Selective Model Order Reduction

Alam

Nieuwoudt

Massoud

2006

2006 IEEE Dallas/Cas Workshop on Design, Applications, Integration and Software

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As process technology continues to scale into the nanoscale regime and overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in characterizing VLSI system performance. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation point by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply multi-shift Krylov subspace methods with uniform interpolation points. I. INTRODUCTIONAggressive feature scaling and increasing operating frequencies greatly impact the performance of high speed integrated circuits [1]. As the complexity of on-chip systems increases, the accurate and efficient modeling of interconnect is vital for estimating and controlling delay, cross-talk noise, and power consumption [2]. Motivated by the expanding complexity of nanoscale integrated circuits, the model order reduction (MOR) of RLC interconnect models has been the focal point of substantial research efforts over the last decade [3]- [6]. MOR provides an invaluable tool for the modeling and design of interconnect in high performance integrated circuits.The methods used for the model order reduction of interconnect fall into two main categories: singular value decomposition (SVD) methods and Krylov subspace projection methods. In SVD methods for linear systems, Hankel-norm approximation, balanced truncation, and singular perturbation methods are well known. The most popular technique is balanced approximation where the primary aim is to generate a balanced representation of the system with same degree of reachability and observability. Balanced approximation based algorithms such as PMTBR [7], [8], PR-TBR [9] and FABT [10], [11] have been proposed. However, SVD methods have high computational complexity with dense computations

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“…As interconnect performance is projected to increasingly dominate the circuit delay, there is significant possibility for design constraint relaxation. [18] and [19] target crosstalk noise and RLC delay pessimism reduction, respectively. Techniques have been presented to account for process variations [23] [22] [21].…”

Section: Introductionmentioning

confidence: 99%

A procedure and program to calculate shuttle mask advantage

et al. 2006

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Abstract-New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spacing between interconnects and interconnect area. Yet, the number of these rules is so few that they are of limited value in circuit or interconnect optimization. A method to infer additional guarantees from the provided guarantees is necessary so that optimization can be optimal. In this paper, we target two problems. First, we present a methodology to infer additional matching guarantees through extracting correlation information from the given limited set of matching guarantees in the design manual. In order to achieve this, we propose a multi-function variant of multi-variate Newton-Raphson method to extract parameters of the proposed dimension-and distancebased process correlation model for interconnects. We propose to use the extracted correlation information to infer a continuum of matching rules through simulation with proposed modifications to the standard capacitance extraction procedure. Secondly, we show how to directly incorporate the inferred interconnect matching guarantees for accurate interconnect optimization in a flexible geometric programming construction. We show how much resource savings are possible through inferring of new matching rules. Applying the inferred mismatch guarantees allows a geometric programming-based H-tree optimization to reduce the clock tree resources 27% on average and up to 56%.

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Expression of Concern: Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance

Cited by 60 publications

References 20 publications

Generation of design guarantees for interconnect matching

Generation of design guarantees for interconnect matching

Dynamic Multi-Point Rational Interpolation for Frequency-Selective Model Order Reduction

A procedure and program to calculate shuttle mask advantage

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