Extended data retention process technology for highly reliable flash EEPROMs of 10/sup 6/ to 10/sup 7/ W/E cycles

Arai, F.; Maruyama, T.; Shirota, R.

doi:10.1109/relphy.1998.670672

Cited by 28 publications

(18 citation statements)

References 3 publications

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“…Generally, the physical mechanism that causes retention failure is leakage current through the tunnel oxide [12], which is due to trap assisted tunneling (TAT) [13]. Basically, electrons from the floating gate tunnel from trap to trap until they escape the oxide.…”

Section: Resultsmentioning

confidence: 99%

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

Oldham

Chen

Friendlich

et al. 2011

IEEE Trans. Nucl. Sci.

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We have compared the data retention of irradiated commercial NAND flash memories with that of unirradiated controls. Under some circumstances, radiation exposure has a significant effect on the retention of flash memories. Introduction. Previously, we compared the endurance reliability of irradiated and unirradiated NAND flash memories, and found no significant difference [1]. An endurance failure would have required enough radiation-induced defects in the tunnel oxide to induce a significant shift in V T . But the unhardened commercial parts used as test samples could be irradiated only to modest doses before they failed for other reasons. It turned out that there would not have been enough radiation-induced defects to cause an endurance failure, until after radiation had caused other failures. However, there was a concern that retention might be more sensitive to radiation, because a retention failure requires only a very low current leakage path. Such a leakage path really only requires a very small number of radiation-induced defects, if they are properly aligned. Therefore, we have compared the retention failure rates for irradiated and unirradiated samples. We find that, under some circumstances, radiation exposure can cause a significant increase in the rate of retention failures in flash memories. We note, however, that flash manufacturers typically specify the endurance and retention characteristics of their products, assuming that error correction software will be used. However, in this test, we did not use error correction, because we were trying to characterize the underlying technology, and not the effectiveness of the error correction. It is likely that, if we had used error correction, the parts would still have met all their reliability specifications. Description of Samples.The samples used in this study are 8G NAND flash memories from Samsung Semiconductor (part number K9F8G08U0A, LDC xxx), and from Micron Semiconductor (part number MT29F8G08ABABA, LDC ###). Both have 4K blocks, with 64 pages per block, with 4Kx8 page organization, plus 64 redundant columns. Each uses a nominal 3.3 V power supply (2.7-3.6 V, full range). The Samsung parts are intended to operate over the industrial temperature range, -40 to +85º C, while the Micron parts are intended for the commercial temperature range, 0-70°C. All NAND flash products typically have a few bad blocks, which have to be screened out. For both manufacturers, the specification is <80 of the 4096 blocks will be bad, but in our experience, a single digit number is more typical. Both the write (Programming) and Erase operations proceed by Fowler-Nordheim tunneling of electrons through the tunnel oxide. Fowler-Nordheim (F-N) injection requires very high fields, and the operation of a charge pump circuit to step up the power supply voltage. F-N injection also introduces damage into the tunnel oxide, contributing to wear-out. It is for this reason, that manufacturers typically guarantee flash memory only for 10 5 (P/E) cycles. This stress-induced...

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Section: Resultsmentioning

confidence: 99%

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

Oldham

Chen

Friendlich

et al. 2011

IEEE Trans. Nucl. Sci.

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“…To keep this contribution negligible, the oxide thickness of Flash cells has barely scaled with the technology generations, going from about 10 nm in the first prototype [3] to about 7-8 nm in the latest nodes [182]. However, experimental data [183][184][185][186][187][188] have demonstrated that, even if the SILC is reduced, there is a small number of cells that can exhibit a high leakage after stress, in analogy with the statistical behavior of RTN. An example of this effect is reported in Figure 16, where thin-oxide (6.5 nm) NOR Flash arrays were cycled heavily (10 4 P/E cycles) before being subjected to positive (left) or negative (right) oxide field to induce a V T shift [189]: note the distribution tails made up of cells featuring an enhanced leakage with respect to the main part of the distribution, whose shift is due to the intrinsic FN tunnelig current.…”

Section: Retention After Cycling and Silcmentioning

confidence: 99%

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

2017

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Abstract:We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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“…SILC causes a severe limitation of the tunnel oxide scaling because a thinner oxide indicates a larger SILC [1]. Furthermore in flash memories anomalously larger leakage current that occurs at a localized spot, causes a severe bit error [2][3][4]. Such a phenomenon is often called anomalous SILC in flash memories.…”

Section: Introductionmentioning

confidence: 99%

Demonstrating distribution of SILC values at individual leakage spots

Inatsuka

Kuroda

Teramoto

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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Stress induced leakage current (SILC) in the order of 10 -17 to 10 -13 A were statistically evaluated by using an advanced test circuit. In this paper, the distribution of SILC was evaluated by changing measurement electric fields, electric stress intensities, device area, and oxide thickness. The distribution of SILC is determined by the current values at individual leakage spots when the device area is sufficiently small. When the electric stress intensity and the measurement field are small, the distribution of logarithm of SILC follows the Gumbel distribution because the maximum current values of the leakage spots determine the gate leakage current in small area MOSFETs. We also evaluated the time-dependent characteristics of SILC in small area MOSFETs. The random telegraph signals of gate leakage current were observed which also indicates the current values of individual leakage spots.

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Extended data retention process technology for highly reliable flash EEPROMs of 10/sup 6/ to 10/sup 7/ W/E cycles

Cited by 28 publications

References 3 publications

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

Effect of Radiation Exposure on the Retention of Commercial NAND Flash Memory

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

Demonstrating distribution of SILC values at individual leakage spots

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