Extended RISC-V hardware architecture for future digital communication systems

Tourres, Mael; Gal, Bertrand Le; Crenne, Jérémie; Coussy, Philippe

doi:10.1109/5gwf52925.2021.00046

Cited by 5 publications

(3 citation statements)

References 41 publications

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“…The RISC-V offers designers an alternative that permits customization and innovation in communication ASIPs. Recent works have designed signal processing [10], [11], error correction coding [43], and radio resource management [44], [54] RISC-V ISA extensions to build flexible and efficient communication ASIPs. Signal processing technologies (such as frequency division multiplexing, beamforming, etc.)…”

Section: Communicationmentioning

confidence: 99%

“…In order to lower hardware costs and accommodate numerous error correction codes (Turbo, LDPC, Polar codes, etc.) that may be changed dynamically, the work [43] extends RISC-V and creates a dynamically re-configurable ASIP. The instruction extensions include absolute value instruction, addition instruction, subtraction instruction, multiplication FIGURE 7.…”

Section: Communicationmentioning

confidence: 99%

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RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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RISC-V is an open-source and royalty-free instruction set architecture (ISA), which opens up a new era of processor innovation. RISC-V has the characteristics of modularization and extensibility, and explicitly supports domain-specific custom extensions. Nowadays, RISC-V is a popular ISA for embedded processors. However, there is still a gap between the capabilities of RISC-V and the requirements of various emerging computing scenarios (e.g., artificial intelligence, cloud computing). Recently, the RISC-V standards organization has continuously introduced new ISA extensions to meet the needs of advanced computing. There are also a variety of novel research proposed customized extensions of RISC-V for certain scenarios. As far as we know, there is a lack of a survey to systematically present the research progress of RISC-V ISA extensions. The goal of this paper is to provide a comprehensive survey on existing works about RISC-V ISA extensions. First, the application scenarios of RISC-V are introduced, and the requirements for ISA extensions are analyzed. Then, we survey the progress of official RISC-V ISA extension specification and recent research on RISC-V ISA extension. Finally, we highlight some possible future research opportunities on the RISC-V ISA extension.INDEX TERMS RISC-V, instruction set architecture, extensions, survey.

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Section: Communicationmentioning

confidence: 99%

Section: Communicationmentioning

confidence: 99%

RISC-V Instruction Set Architecture Extensions: A Survey

Cui

Qian

2023

IEEE Access

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“…The customization of communication interface operation is not commonly addressed by systems designers. There is some effort invested in the development of RSIC-V extensions targeted at digital communications, as presented in paper [ 26 ]. The authors develop specific instructions that lead to a reduction in clock cycles (needed for certain algorithms involved in 5G communications) of up to 47%, with an area overhead of 25%.…”

Section: Related Workmentioning

confidence: 99%

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool

Popovici

Stan

2023

Micromachines

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Network Diagnosis Tools with industrial-grade quality are not widely available for common users such as researchers and students. This kind of tool enables users to develop Distributed Embedded Systems using low-cost and reliable setups. In the context of RISC-V Extensions and Domain-Specific Architecture, this paper proposes a Real-Time RISC-V-based CAN-FD Bus Diagnosis Tool, named RiscDiag CanFd, as an open-source alternative. The RISC-V Core extension is a CAN-FD Communication Unit controlled by a dedicated ISA Extension. Besides the extended RISC-V core, the proposed SoC provides UDP Communication via Ethernet for connecting the proposed solution to a PC. Additionally, a GUI application was developed for accessing and using the hardware solution deployed in an FPGA. The proposed solution is evaluated by measuring the lost frame rate, the precision of captured frames timestamps and the latency of preparing data for Ethernet communication. Measurements revealed a 0% frame loss rate, a timestamp error under 0.001% and an acquisition cycle jitter under 10 ns.

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