The 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 2021
DOI: 10.1145/3431920.3439470
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Extending High-Level Synthesis for Task-Parallel Programs

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Cited by 7 publications
(5 citation statements)
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“…The OCaml heap and stack can be stored either in the on-chip memory of the target FPGA (for small programs) or in the external memory (SDRAM) of the board. In both cases, access is provided by means of an interconnection bus 7 . This bus also supports data transfers between the custom components and the binary code executed by the processor.…”
Section: Our Contributions Arementioning
confidence: 99%
See 2 more Smart Citations
“…The OCaml heap and stack can be stored either in the on-chip memory of the target FPGA (for small programs) or in the external memory (SDRAM) of the board. In both cases, access is provided by means of an interconnection bus 7 . This bus also supports data transfers between the custom components and the binary code executed by the processor.…”
Section: Our Contributions Arementioning
confidence: 99%
“…Aparapi [24] and GVM [12] implement the JVM in OpenCL. TAPA [7] is a framework for task parallelism targeting OpenCL. TornadoVM [22] compiles specially annotated Java code to OpenCL.…”
Section: Introductionmentioning
confidence: 99%
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“…There are a number of tasking systems that have emerged in the recent years targeting different layers of the application, from low-level assembly layer [35], and parallelizing compilers [49] to high level tasking frameworks [13]. A complete review of the current state-of-the-art tasking environments is outside the scope of this section.…”
Section: Related Workmentioning
confidence: 99%
“…Investigating the cause of this overhead and optimizing the abt and Fig. 13 Effect of scheduling limit for the second approach using the tbb back-end. Right zoom-in in range 0.5-2.0…”
Section: Performance Evaluationmentioning
confidence: 99%