Extensible linear floating point SIMD neurocomputer array processor

Means, R.W.; Lisenbee, L.

doi:10.1109/ijcnn.1991.155243

Cited by 17 publications

(9 citation statements)

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“…Most other systems, even if the implementation is not described explicitly, aim at the same kind of parallelization. This is the case both for machines based on commercial processors (e.g., RAP [19], MUSIC [20]) and systems with custom processing elements (e.g., SNAP [18], TNP [12]). The limit of this approach is reached when one processing unit is used per neuron.…”

Section: Version Winner Selection Weight Updatementioning

confidence: 99%

Modified self-organizing feature map algorithms for efficient digital hardware implementation

Ienne

Thiran

Vassilas

1997

IEEE Trans. Neural Netw.

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This paper describes two variants of the Kohonen's self-organizing feature map (SOFM) algorithm. Both variants update the weights only after presentation of a group of input vectors. In contrast, in the original algorithm the weights are updated after presentation of every input vector. The main advantage of these variants is to make available a finer grain of parallelism, for implementation on machines with a very large number of processors, without compromising the desired properties of the algorithm. In this work it is proved that, for one-dimensional (1-D) maps and 1-D continuous input and weight spaces, the strictly increasing or decreasing weight configuration forms an absorbing class in both variants, exactly as in the original algorithm. Ordering of the maps and convergence to asymptotic values are also proved, again confirming the theoretical results obtained for the original algorithm. Simulations of a real-world application using two-dimensional (2-D) maps on 12-D speech data are presented to back up the theoretical results and show that the performance of one of the variants is in all respects almost as good as the original algorithm. Finally, the practical utility of the finer parallelism made available is confirmed by the description of a massively parallel hardware system that makes effective use of the best variant.

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Section: Version Winner Selection Weight Updatementioning

confidence: 99%

Modified self-organizing feature map algorithms for efficient digital hardware implementation

Ienne

Thiran

Vassilas

1997

IEEE Trans. Neural Netw.

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“…Some of these systems include the NAP [4], the RVIP [5], the IMAP [6], [7], the NAC [8] and the SLAP [9]. The mesh architectures are multiprocessor systems, with several processors interconnected as a (2D) array.…”

Section: Related Workmentioning

confidence: 99%

SMAC: A VLSI Architecture for Scene Matching

1998

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“…The processors in SIMD system are much simpler than those in SPMD system because they do not have to fetch and decode instructions. Examples of SIMD neurocomputers include the CNAPS systems [19] from Adaptive Solutions and the SNAP [36] system from HNC. The neurochip N6400 is the basic building block of the CNAPS system and consists of 64 processing elements (or processing nodes PN) connected by a broadcast bus.…”

Section: Simd Processor Arraysmentioning

confidence: 99%