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The edit distance between two strings al, . . .,a, rind b l , . . . , b, is the minimum cost s of a sequence of editing operations (insertions, deletions and substitutions) that convert one string into the other. This paper presents a linear systolic array for computing the edit distance between two strings over a given alphabet. A n en,coding scheme is proposed which reduces the number of bats required t o represent a state in the computation. The architecture is a parallel realization of the standard dynamic programming algorithm proposed b y Wagner and Fischer, and can perform approximate string matching for variable edit costs. More importantly, the architecture does not place any constraint on the lengths of the strings that can be compared. It makes use of simple basic cells and requires regular nearest-neighbor communication, which makes it suitable f o r VLSI implementation. A protot,ype of this array is currently being built at the Unaversity of South Florida. I IntroductionIn approximate string matching (also known as the string-to-string correction problem , a similarity meabetween two strings. This distance is cornputed using three editing operations, substitution, deletion and insertion. Each of these operations has a cost associated with it. The objective of approximate string matching is to determine the minimum cost required to transform one string into another using these three editing operations.String comparison is an important task, and has aplications in information retrieval, pattern recognition bl 4,51 , error correction, molecular genetics [3,8], and tcxt search and edit systems. Recent advances in Very Large Scale Integration (VLSI) technology have made the development of special purpose architectures and hardware algorithms for complex, computationally intensive algorithms possible. High packaging densities, decrease in gate delays, decreasing fabrication costs, powerful design automation tools, and reliable and fault-tolerant design strategies are some of the advantages of present day VLSI technology.In this paper, we present a linear, systolic array for approximate string matching. The architecture is a sure called the edit distance nee d s to be computed --'This research has been supported in part by the National Svience Foundation Grant No.MIP-9010358.parallel realization of the dynamic programming algorithm proposed by Wagner and Fischer [7]. An encoding scheme is proposed which minimiees the data flow between adjacent processors. More significantly, the array can perform edit distance computations for variable edit costs, and does not impose any constraint on the lengths of the strings that can be processed.In the next section, the merits and demerits of other VLSI architectures proposed in the literature for a p proximate string matching are discussed. Section 3 describes the proposed encoding scheme. In Section 4, a detailed description of the proposed systolic array architecture is presented. A partitioning scheme that can be used when the problem size is too large for the array...

An I/O transceiver for scalable multiprocessor systems with 1.25Gb/s parallel bandwidth and 7.7ns latency performs as a plesiochronous link and compensates for skin-effect cable loss and inter-wiring skew across 20m cable connections [ 11. Phase-interpolator-based clock recovery integrates multiple I/O links that can tolerate slight differences in frequencies between incoming and internal reference clocks. A differential partial-response detection (DPRD) receiver ensures low latency equalization for skineffect cable loss of up to 10dB. The receivers are equipped with deskew circuitry to tolerate up to 6.411s inter-wiring skew for 20 data bits. The data rate, driver output level, and receiver clock phase are adjusted automatically by a logic sequencer, basic control, which maximizes data rate and minimizes power consumption without external manual adjustment, adapting from onboard PCB traces to 20m twisted-pair cables.The drivedreceiver arrays have 19 data signals (including 2-EDC signals and logic signaling bit), physical layer signaling bit, and clock signal, which are differential (Figure 10.3.1). 625MHz and 312.5MHz, are provided by a single core PLL to all I/O interfaces on the chip. Data from the core logic, which is synchronized with the 312.5MHz core clock, is applied to the driver unit, which performs 440-1 multiplexing to output a 1.25Gb/s data stream. The bit-to-bit clock phase is adjusted by the receiver interpolator during power-on initialization. The clock-recovery loop in the clock receiver tracks the incoming clock and outputs a fastlslow code corresponding to the phase difference between incoming/ internal clock signals. The same code controls all interpolators, enabling them to track the incoming clock. The incoming 1.25Gb/ s data is subject to 1-to-4 demultiplexing and alignment to a single incoming clock through retiming and deskewing circuits.The driver employs push-pull output stages with high-output impedance to render current consumption lower than that used in conventional resistor-load transmitters ( Figure 10.3.2). To match output impedance with cable impedance, the output stages are parallel-terminated by on-chip CMOS transfer-gate terminators. The terminator resistance is adjusted to within 25% of the external reference resistor by feedback control. The output current is digitally-controlled in the range from 0 to 21mA by a 4b DAC and adjusted in a self-configuring link-initialization sequence, which ensures 250mV signal at the receivers. Clock skew fluctuation from 2.25V -2.75V supply variation is estimated to be 160ps; within DPRD receiver data-clock skew tolerance.After being terminated, differential inputs are applied to two-way interleaving receivers (Figure 10.3.3). DPRD, a type of a capacitorcoupled auto-zero comparator, performs 1-xD operation (the x being a positive value less than unity and D being the one bit time delay operator) to eliminate intersymbol interference (ISI) and provide equalization compensating for the frequency-dependent attenuation in long cables [2].At the...

The recognition of patterns is an important task in robot and computer vision. The patterns themselves could be one- or two-dimensional, depending upon the application. Pattern matching is a computationally intensive and time consuming operation. The design of special purpose hardware could speed up the matching task considerably, making real-time responses possible. Advances in parallel processing and VLSI technologies have made it possible to implement inexpensive, efficient and very fast custom designs. Many approaches and solutions have been proposed in the literature for hardware implementations of pattern matching techniques. In this paper, we present a detailed overview of some of the important contributions in the area of hardware algorithms and architectures for pattern matching.

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