Extracting Useful Computation from Error-Prone Processors for Streaming Applications

Yetim, Yavuz; Martonosi, Margaret; Malik, Sharad

doi:10.7873/date.2013.055

Cited by 19 publications

(11 citation statements)

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“…Our baseline system is a 32-bit Intel x86 architecture simulating 10 processor cores. Our simulator models hardware errors through architectural error injection and implements the PPU cores described in [32].…”

Section: Experimental Methodologymentioning

confidence: 99%

“…For example, architectures proposed in [18,32] handle control-flow and memory-addressing errors when they may cause crashes or hangs. The reliability analysis proposed in [4] allows cores that may have bounded control-flow and memory addressing errors in its execution model.…”

Section: Tolerating Hardware Errorsmentioning

confidence: 99%

“…We now describe CommGuard's integration with the PPU cores in [32]. The application is divided into coarse-grained (potentially nested) control-flow regions termed scopes.…”

Section: Guided Execution Management and Its Integration With Commguardmentioning

confidence: 99%

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CommGuard

Yetim

Malik

Martonosi

2015

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems

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As semiconductor technology scales towards ever-smaller transistor sizes, hardware fault rates are increasing. Since important application classes (e.g., multimedia, streaming workloads) are data-error-tolerant, recent research has proposed techniques that seek to save energy or improve yield by exploiting error tolerance at the architecture/microarchitecture level. Even seemingly error-tolerant applications, however, will crash or hang due to control-flow/memory addressing errors. In parallel computation, errors involving inter-thread communication can have equally catastrophic effects.Our work explores techniques that mitigate the impact of potentially catastrophic errors in parallel computation, while still garnering power, cost, or yield benefits from data error tolerance. Our proposed CommGuard solution uses FSMbased checkers to pad and discard data in order to maintain semantic alignment between program control flow and the data communicated between processors. CommGuard techniques are low overhead and they exploit application information already provided by some parallel programming languages (e.g. StreamIt). By converting potentially catastrophic communication errors into potentially tolerable data errors, CommGuard allows important streaming applications like JPEG and MP3 decoding to execute without crashing and to sustain good output quality, even for errors as frequent as every 500µs.

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Section: Experimental Methodologymentioning

confidence: 99%

Section: Tolerating Hardware Errorsmentioning

confidence: 99%

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CommGuard

Yetim

Malik

Martonosi

2015

Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Effective use of AC requires judicious selection of approximable code/data portions and approximation strategy, since uniform approximation can produce unacceptable quality loss [Ranjan et al 2015;Sartori and Kumar 2013]. Even worse, approximation in control flow or memory access operations can lead to catastrophic results such as segmentation fault [Yetim et al 2013]. Further, careful monitoring of output is required to ensure that quality specifications are met, since large loss makes the output unacceptable or necessitates repeated execution with precise parameters.…”

Section: Introductionmentioning

confidence: 99%

A Survey of Techniques for Approximate Computing

2016

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Approximate computing trades off computation quality with effort expended, and as rising performance demands confront plateauing resource budgets, approximate computing has become not merely attractive, but even imperative. In this article, we present a survey of techniques for approximate computing (AC). We discuss strategies for finding approximable program portions and monitoring output quality, techniques for using AC in different processing units (e.g., CPU, GPU, and FPGA), processor components, memory technologies, and so forth, as well as programming frameworks for AC. We classify these techniques based on several key characteristics to emphasize their similarities and differences. The aim of this article is to provide insights to researchers into working of AC techniques and inspire more efforts in this area to make AC the mainstream computing approach in future systems.

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“…Those units manage the control flow and execute critical operations, while error resilient computations are offloaded to unreliable hardware. The total area and power costs related to hardening are thus significantly reduced [31,55]. A different approach is found in [51], where the authors propose a vector processor in which the "quality-level" of each operation can be set at the software level, thanks to a specific Instruction Set Architecture.…”

Section: Processor-level Techniquesmentioning

confidence: 99%

Energy-Efficient Digital Processing via Approximate Computing

Pagliari

Poncino

Macii

2016

Smart Systems Integration and Simulation

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While the most characteristic feature of a smart system is its capability of sensing a set of environmental quantities and actuating appropriate actions in response to those signals, it is obvious that a significant part of its functional operations is involved with the elaboration of the information carried by the signals [14]. This elaboration is usually done after converting the analog, asynchronous environmental signals into the digital domain.Part of the smartness of a smart system is therefore expressed in the autonomous and transparent operation based on closed loop control and predictive capabilities, as well as improved signal processing technologies. The former functions are normally carried out by a micro-controller or processor core, whereas the latter ones rely on either a digital signal processor (DSP) or an application-specific integrated circuit (ASIC). Hybrid architectures, that combine one or more general purpose CPUs with one or more hardware accelerators are also increasingly popular [11].Such "processing" dimension, coupled with the energy-autonomous nature of these systems put significant emphasis on their energy efficiency [4,12]. Measures for reducing energy (and power) consumption vary according to the engineering domain of the component being considered. In the computing subsystem, classical low-power techniques for processors and digital circuits can be fruitfully exploited [35]. In this chapter, however, we focus on the explicit signal processing task and show how we can effectively leverage an emerging design paradigm called approximate computing [20,52].

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Extracting Useful Computation from Error-Prone Processors for Streaming Applications

Cited by 19 publications

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CommGuard

CommGuard

A Survey of Techniques for Approximate Computing

Energy-Efficient Digital Processing via Approximate Computing

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