Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Kimura, Mutsumi

doi:10.1016/j.sse.2011.05.002

Cited by 15 publications

(11 citation statements)

References 22 publications

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“…During the t r transition edge, as V g swings from 0 V to a high positive voltage, p-type TFT switches from near the flat-band condition to the accumulation. However, electrons accumulation cannot follow the pulse switching because of the slow response time of the establishment of accumulation as few electrons can be supplied into the channel from the p + source and drain, which is also confirmed by the observation of depletion-more rather than accumulation-mode CV characteristic in the low frequently CV curves measured on poly-Si TFTs [31]. As the channel is still neutral, the transient positive V g will be applied to the junctions between the channel and the S/D as a reverse bias, where ε x is established and increases with time during t r [9], [21].…”

Section: B Degradation Mechanismmentioning

confidence: 73%

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Zhang

Wang

2014

IEEE Trans. Electron Devices

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Two-stage degradation of p-type polycrystalline silicon thin-film transistors under dynamic positive bias temperature (PBT) stress is reported for the first time. ON-state current (I ON ) gradually increases in the first degradation stage while dramatically drops in the second degradation stage, which are, respectively, due to the channel length shortening effect, caused by electrons trapping into the gate oxide, and grain boundary potential barrier buildup, caused by dynamic hotcarrier-induced traps generation. The transition from the first to the second degradation stage is clarified, in which the pulse peak duration plays a key role. Longer pulse peak duration is preferred to suppress the dynamic PBT stress-induced degradation.Index Terms-Dynamic stress, hot carrier (HC), impact ionization, poly-Si, positive bias temperature instability (PBTI), thin-film transistor (TFT).

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Section: B Degradation Mechanismmentioning

confidence: 73%

Two-Stage Degradation of p-Type Polycrystalline Silicon Thin-Film Transistors Under Dynamic Positive Bias Temperature Stress

Zhang

Wang

2014

IEEE Trans. Electron Devices

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“…One of the key properties of polysilicon is its trap density, whose value has been estimated by several works, based on either direct optical or electrical experimental measurements [ 66 , 67 , 68 , 69 , 70 , 71 , 72 , 73 , 74 ] or via numerical device simulations [ 75 , 76 , 77 , 78 , 79 ]. Many of such results point to a double-exponential energy distribution of donor-like and acceptor-like states of the form (for acceptor-like states in the upper half of the energy gap):

where the reported range for the acceptor-like states parameters is listed in Table 1 .…”

Section: Polysilicon Conductionmentioning

confidence: 99%

Random Telegraph Noise in 3D NAND Flash Memories

et al. 2021

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In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND Flash arrays. The main features of such arrays resulting from their mainstream integration scheme are first discussed, pointing out the relevant role played by the polycrystalline nature of the string silicon channels on current transport. Starting from that, experimental data for RTN in 3D arrays are presented and explained via theoretical and simulation models. The attention is drawn, in particular, to the changes in the RTN dependences on the array working conditions that resulted from the transition from planar to 3D architectures. Such changes are explained by considering the impact of highly-defective grain boundaries on percolative current transport in cell channels in combination with the localized nature of the RTN traps.

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“…9 First, the potential gradient at the front interface in the channel layer ((/ x ) s ) is calculated using Gauss's law.…”

Section: Gate Insulatormentioning

confidence: 99%

“…n a is calculated using the following equation. n a =ndx [9] Next, by comparing  s and n a between the experiment and calculation,   is determined and D fi is extracted. q it is calculated using Gauss's law.…”

Section: Gate Insulatormentioning

confidence: 99%