Extrinsic gate capacitance compact model for UTBB MOSFETs

Abstract

Ultra-thin body and buried oxide transistors have gained attention as candidates for near future CMOS technology nodes. Recent studies have pointed out that the total parasitic gate capacitance becomes an important concern for very-high frequency performance. In this paper a semi-analytical model to describe the total extrinsic gate capacitance for ultrathin silicon body and buried oxide transistors is presented. The developed model considers the main technological parameters and has been verified by finite-element numerical simulations as well as by comparison with experimental measurements. The relative weight of the main parasitic components is addressed as well as their impact over the current gain cut-off frequency. Finally, the possibility to improve the cut-off frequency by about 35% due to the reduction of the parasitic gate capacitance is highlighted.

Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

“…Many reported literatures depict the usage of air-pockets as spacers (commonly known as air-spacers) to further increase the performance of the transistors and their applications in circuits, by reducing the gate parasitic capacitances [26][27][28][29][30][31][32]. NSTs can also incorporate air-pockets as inner spacers using the process steps explained in literature [33][34][35].…”