Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Abstract

h TWO-AND-A-HALF-DIMENSIONAL THROUGH SILICON interposers (TSIs) provide an attractive packaging opportunity enabling the integration of off-the-shelf heterogeneous 2-D integrated circuit (IC) components (i.e., logic and memory) [1] with a plausible extension to build an entire smart system consisting of logic, memory, sensors, photonics, etc., on 2.5-D ICs. While the technology is undisputedly attractive, 2.5-D TSI technology cost is a critical factor to adopt the technology in high volume manufacturing. Traditionally, fabrication of 2.5-D TSI consists of through silicon vias (TSVs), frontside Cu-damascene interconnects, frontside microbumps, backside reveal (BSR) processing followed by the fabrication of larger backside solder bump before the wafers are passed to the interposer assembly on package. 2.5-D TSI cost [2], [3] reduction can be achieved by increasing throughput and reusing the existing semiconductor and outsourced semiconductor assembly and test (OSAT) tools. We investigate the following options to reduce the TSI cost: 1) by adapting polymer-based Cu-RDL lines; 2) leveraging GHI-lithography; and 3) eliminating the organic substrate and placing the 2.5-D TSI directly on the PCB.Two-and-a-half-dimensional TSIs with Cudamascene interconnects are costlier due to chemical mechanical polishing (CMP) costs associated with the fabrication of frontside Cu-damascene interconnects. Polymer-based Cu-RDL interconnects provide a CMPless low-cost fabrication alternative enabling OSATs to fabricate and assemble a 2.5-D low-cost through silicon interposer (LC-TSI) in low-cost infrastructure facilities. Additionally, the cost reduction in 2.5-D TSI fabrication and assembly can be achieved by adapting the GHI-line lithography providing enhanced Editor's notes: Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.throughput. Moreover, placement of 2.5-D TSI directly on the package eliminating an organic substrate reduces the 2.5-D TSI cost even further.Technology specifications and challenges along with LC-TSI fabrication and assembly flow are detailed in the Technology specifications and challenges section and the 2.5-D LC-TSI fabrication and assembly flow section, respectively. Electrical characterization and measurement results are elaborated on in the Electrical characterization and measurements section. Results also include the early reliability test results to evaluate suitable polymer dielectric through unbiased highly accelerated stress test (uHAST). Technology specifications and challengesTypical applications for 2.5-D TSI include SoC/GPU/FPGA integration with different classes of memories such as WIDEIO, high bandwidth memory (HBM), etc. For example, Li et al.[1] detail FPGA as well as guest-die-based TSI integration. Cross section of 2.5-D LC-TSI technology with...