Fabrication and Characterization of 4H-SiC pn Diode with Field Limiting Ring

Abstract

4H-SiC pn diodes with field limiting rings(FLRs) were fabricated and characterized. The dependences of reverse breakdown voltage on the number of FLRs, the distance between p-base main junction and first FLR, and activation temperatures, were investigated. Al and B ions were implanted and activated at high temperature to form p-base and p+ region in the n-epilayer, respectively. We have obtained up to 1790V of reverse breakdown voltage in the pn diode with two FLRs on 10µm thick epilayer. The differential on-resistances of the fabricated diode are 5.3mΩcm 2 at 100A/cm 2 and 2.7mΩcm 2 at 1kA/cm 2 , respectively. All pn diodes with FLRs have higher avalanche breakdown voltages than those without an FLR. This study reveals that the FLR edge termination techniques for SiC pn diodes can provide high blocking voltage as well as low on-resistance.

Realistic simulation on reverse characteristics of SiC/GaN p-n junctions for high power semiconductor devices

“…Moreover, to grow a thicker drift layer, longer time for high temperature HTCVD growth is required when fabricating the original wafer, which will also lead to a larger defect density. Therefore, a linear relationship for trap density (cm -3 ) in terms of the doping and the drift layer thickness is assumed to capture these effects as: (2) where N (cm -3 ) is the drift layer doping concentration, W ( m) is the thickness of drift layer, and account for parameters of trap density induced by implantation and growth respectively. The value of these two parameters were obtained by matching the simulated data of reported devices to the experimental data.…”

“…Wide bandgap materials provide high critical electric field, which is suitable to sustain high breakdown voltage [1][2][3][4]. The maturing technology in the production of single crystal SiC substrates and its process technologies enable the successful fabrication of extremely high voltage SiC devices.…”

Modification of Surface Layer during High Temperature Annealing and its Effects on the SiC Diode Characteristics

“…The width of the FLRs was fixed at 3 µm and the space between FLRs was varied from 3 µm to 7.5 µm. For fabrication of SiC PiN diodes, B and Al ions were implanted at 650 o C. Post ion implantation annealing temperature was fixed at 1650 o C. P-well and FLRs were simultaneously formed 700nm deep with concentration of 5 × 10 17 cm -3 by B ion implantation [1]. Al ions were implanted 20nm deep with the concentration of 1 × 10 20 cm -3 for good ohmic contact with Ni cathode.…”

“…Ion implantation process becomes essential for fabrication of SiC devices. The p/n junction is needed not only for pn diode but also for the formation of edge termination structure such as field limiting rings, junction termination extension, etc [1]. Therefore it is necessary even for the fabrication of the high voltage SiC Schottky diodes.…”

“…The very high temperature up to 1700 o C can cause roughening of SiC surface. Morphological evolution of SiC surface during high temperature annealing was frequently reported and many researchers have endeavored to reduce and/or suppress it [1][2][3][4]. It is reported that the roughening of surface deteriorates ideality factor and Schottky barrier height of the SiC Schottky diodes [5].…”