Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer

Lee, Kwang Hong; Bao, Shuyu; Chong, Gang Yih; Tan, Yew Heng; Fitzgerald, Eugene A.; Tan, Chuan Seng

doi:10.1063/1.4895487

Cited by 56 publications

(32 citation statements)

References 14 publications

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“…Actually, in conventional SOI fabrication, a high temperature annealing process is always conducted to cure the defects in Si layer [20]. Furthermore, high temperature annealing has also shown great effectiveness to reduce the dislocations in a GOI wafer fabricated by transferring a Ge epitaxial film grown on a Si substrate [21,22]. Thus, we have investigated the thermal annealing impact on the crystal quality of the Ge layer on the GOI substrate fabricated by Ge bulk wafer bonding and ioncutting.…”

Section: Effect Of Thermal Annealing On Ge-on-insulatormentioning

confidence: 99%

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Kang

Takenaka

et al. 2016

Materials Science in Semiconductor Processing

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Section: Effect Of Thermal Annealing On Ge-on-insulatormentioning

confidence: 99%

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Kang

Takenaka

et al. 2016

Materials Science in Semiconductor Processing

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“…The ProTEK B3-25 protective coating was removed in O 2 plasma with a power of 800 W. The details of the fabrication process can be found in the Ref. 19.…”

Section: 6mentioning

confidence: 99%

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

et al. 2015

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A method to remove the misfit dislocations and reduce the threading dislocations density (TDD) in the germanium (Ge) epilayer growth on a silicon (Si) substrate is presented. The Ge epitaxial film is grown directly on the Si (001) donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001) handle wafer to form a germanium-on-insulator (GOI) substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

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“…In contrast to the technical maturity of the Geon-SOI platform, the Ge-OI platform is recently gaining attention for both advanced electronic 41 and photonic 42,43,44 applications. In this work, the Ge-OI was formed on a 200-mm Si (100) wafer via Ge-on-Si epitaxy, bonding, and layer transfer, using silicon dioxide (SiO 2 ) as the intermediate insulator layer 45 .…”

Section: Recessed Sin X Stressor For Enhanced and Uniform Mechanical mentioning

confidence: 99%

Strain-enabled ultra-broadband Ge-based photonic devices for low-cost integration in PICs

Lin

Wen

et al. 2020

Preprint

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Photonic-integrated circuits (PICs) have become one of the most promising solutions to the burgeoning global data communication and are being envisioned to have revolutionary impact in many other emerging fields. This outlook requires future PICs to be significantly more broadband and cost-effective. The current germanium (Ge)-based active photonic devices in PICs are thus facing a new bandwidth-cost trade-off. Here, we demonstrate ultra-broadband, high-efficiency Ge photodetectors up to 1,630 nm operation wavelength and Ge0.99Si0.01 electro-absorption (EA) modulator arrays with an operating range of ~100 nm from 1,525 to 1,620 nm, using a CMOS-compatible recess-type silicon nitride (SiNx) stressor. The broadband operation could facilitate a wide (>100 nm) window for low-cost Ge modulator-detector co-integration, requiring only a single step of Ge epitaxy and two different SiNx depositions. The broad modulation and co-integration coverage can be entirely shifted to shorter (~1,300 nm) and longer (>1,700 nm) wavelengths with small amounts of Si or tin (Sn) alloying. This proof-of-concept work provides a pathway for PICs towards future low-cost and high-data-capacity communication networks, immediately accessible by designers through foundries.

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Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer

Abstract: Fabrication and characterization of germanium-on-insulator through epitaxy, bonding, and layer transfer

Cited by 56 publications

References 14 publications

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

Strain-enabled ultra-broadband Ge-based photonic devices for low-cost integration in PICs

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