Fabrication and Characterization of Nanonet-Channel LTPS TFTs Using a Nanosphere-Assisted Patterning Technique

Abstract

We present the fabrication and electrical characteristics of nanonet-channel (NET) low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs) using a nanosphere-assisted patterning (NAP) technique. The NAP technique is introduced to form a nanonet-channel instead of the electron beam lithography (EBL) or conventional photolithography method. The size and space of the holes in the nanonet structure are well controlled by oxygen plasma treatment and a metal lift-off process. The nanonet-channel TFTs show improved electrical characteristics in terms of the ION/IOFF, threshold voltage, and subthreshold swing compared with conventional planar devices. The nanonet-channel devices also show a high immunity to hot-carrier injection and a lower variation of electrical characteristics. The standard deviation of VTH (σVTH) is reduced by 33% for a nanonet-channel device with a gate length of 3 μm, which is mainly attributed to the reduction of the grain boundary traps and enhanced gate controllability. These results suggest that the cost-effective NAP technique is promising for manufacturing high-performance nanonet-channel LTPS TFTs with lower electrical variations.

The Design and Fabrication of Large-Area Under-Screen Fingerprint Sensors with Optimized Aperture and Microlens Structures

“…In particular, the LTPS image sensor performs better than the IGZO image sensor in terms of PPI and has electron mobility and even advantages in manufacturing costs. However, compared to the on/off current ratio of the IGZO image sensor of up to 10 7 [7], the LTPS image sensor has a current ratio of only about 10 5 to 10 6 [8][9][10], which leads to a worse photosensitive image in fingerprint image detection. If we want to solve this issue, careful optical design is necessary to compensate for the photosensitivity problem.…”