Fabrication and characterization of nonvolatile organic thin film memory transistors operating at low programming voltages

Fakher, S J; Mabrooka, M.F.

doi:10.1051/epjap/2012120288

Cited by 6 publications

(7 citation statements)

References 26 publications

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“…A clockwise hysteresis loop is observed for the output characteristic, whilst a counter-clockwise hysteresis loop is observed for the transfer characteristic when the gate voltage sweeps from positive to negative voltages. Such hysteresis loops are in satisfactory agreement with our recent studies for a gold thin layer [26] and for gold nanoparticles [30]; these results are consistent with other reports [31] for CNT based TFMT devices.…”

Section: Resultssupporting

confidence: 93%

“…Otherwise, the hysteresis becomes a big advantage when using the CNTFETs as memory devices instead. In recent progress, we have reported floating gate memory devices based on the MIS and transistor structure, using a thin film of Au layer [8,26] where there is a clear hysteresis in their electrical characteristics for the transistor and also for the capacitance–voltage ( C–V ) characteristics of MIS structures. On the other hand, there is little or no hysteresis for the control devices of these structures.…”

Section: Introductionmentioning

confidence: 99%

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Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

et al. 2016

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Abstract:The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs), metal-insulator-semiconductor (MIS) and thin film transistor (TFT) structures, using poly(methyl methacrylate) (PMMA) as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of SWCNTs, embedded within the insulating layer, were used as the floating gate. SWCNTs-based memory devices exhibited clear hysteresis in their electrical characteristics (capacitance-voltage (C-V) for MIS structures, as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics, the shifts in the threshold voltage of the transfer characteristics, and the flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the SWCNTs floating gate. Under an appropriate gate bias (1 s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses as low as 1 V resulted in clear write and erase states.

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Section: Resultssupporting

confidence: 93%

Section: Introductionmentioning

confidence: 99%

Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

et al. 2016

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“…Figure 9 represents the relative energy diagrams for the materials used in the fabrication of the GO-based memory device. The work function for Au and Al are 5.1 and 4.3 respectively [24], while, the highest-occupied molecular orbital (HOMO) and the lowest-unoccupied molecular orbital (LUMO) levels of TIPS-pentacene are −5.3 eV and −3.4 eV) respectively [25]. As discussed earlier, the counter-clockwise hysteresis direction of the transfer characteristics in Figure 4b indicates that charging and discharging of the memory transistor take place through the semiconductor.…”

Section: Resultsmentioning

confidence: 99%

Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors

et al. 2019

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).

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“…The energy band diagram of the Al/PVP/AuNPs/PVP/ pentacene/Au structure were considered for investigation. Figure 9 represents the relative energy diagrams for the materials used in the fabrication of the memory device, where the work functions for Al and Au are 4.3 and 5.1 eV, respectively [12]. The highest-occupied molecular orbital (HOMO) and the lowest-unoccupied molecular orbital (LUMO) levels of pentacene are − 5 and − 3 eV [12], respectively.…”

Section: Resultsmentioning

confidence: 99%

“…The morphology of the evaporated pentacene is dependent on the surface energy of the substrate which is grown on. Because of simple processing via spin-coating or casting, and ready tuning of the surface chemical properties [11], polymeric dielectrics have recently been employed as OTFT gate insulators that afford superior performance in pentacene-based OTFTs versus those fabricated with SiO 2 insulators [12]. The low surface energy of poly4-vinylphenol (PVP) was reported by other researchers to be the most suitable as an organic dielectric for the growth of pentacene thin film [13].…”

Section: Introductionmentioning

confidence: 99%

High capacity organic memory structures based on PVP as the insulating layer

Fakher

Alias

Sayers

et al. 2018

J Mater Sci: Mater Electron

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The electrical behaviour of organic memory structures based on gold nanoparticles (AuNPs) and poly 4-vinylphenol as the gate dielectric are reported in this work. Metal-insulator-semiconductor (MIS) and thin film transistor structures were used to fabricate the control and memory devices. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of AuNps embedded within the insulating layer were used as the floating gate. All memory devices exhibited clear hysteresis in their electrical characteristics [capacitance-voltage (C-V) for MIS structures as well as output and transfer characteristics for transistors]. Both structures were shown to produce reliable and large memory windows by virtue of high capacity. The hysteresis in the output and transfer characteristics and shifts in the threshold voltage of the transfer characteristics as well as flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the AuNPs floating gate. Memory window of 38 V was achieved by scanning the applied voltage of the MIS structure between 40 and − 40 V. Similarly, a memory window of 27 V was achieved for the TFT-based memory structure. Under an appropriate gate bias of 1 s pulses, the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses of as low as 5 V resulted in a clear write and erase states.

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Fabrication and characterization of nonvolatile organic thin film memory transistors operating at low programming voltages

Cited by 6 publications

References 26 publications

Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

Single-Walled Carbon-Nanotubes-Based Organic Memory Structures

Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors

High capacity organic memory structures based on PVP as the insulating layer

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