Fabrication and Electrical Characterization of 3D Vertical Interconnects

Newman, Michael; Muthukumar, Sriram; Schuelein, M.; Dambrauskas, Tadas; Dunaway, Pat; Jordan, J.; Kulkarni, S.; Linde, C.D.; Opheim, T.A.; Stingel, R.A.; Worwag, W.; Topic, L.A.; Swan, Johanna

doi:10.1109/ectc.2006.1645676

Cited by 27 publications

(17 citation statements)

References 5 publications

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“…Here the formation of HF is not taken into account to simplify the calculation of fluoride species concentration. Due to the low acidity of H 2 27 Considering the fact that H + is also involved in the reduction of H 2 O 2 (Eq. 1), the relation between c(H + ) and etching depth indicates that the dissolution of oxidized Si (Eq.…”

Section: Resultsmentioning

confidence: 99%

“…For example, deep trenches are the core structures in the microelectromechanical systems; 1 deep holes serve as the interconnect routes in the emerging 3D integration technology in microelectronic packaging. 2 Most of these HAR structures are fabricated by selective removal of certain volume of Si from the bulk Si substrate, which is generally referred to as the etching of Si. Until now, the major applicable Si etching method for HAR structures fabrication is the deep reactive ion etching (DRIE).…”

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confidence: 99%

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Charge Transport in Uniform Metal-Assisted Chemical Etching for 3D High-Aspect-Ratio Micro- and Nanofabrication on Silicon

Zhao

Wong

2015

ECS J. Solid State Sci. Technol.

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Recently, metal-assisted chemical etching (MaCE) has been proposed as a promising method for micro-and nanostructures fabrication on silicon (Si) with high aspect ratio, high geometric uniformity and low cost. In MaCE, electron holes (h + ) are injected into Si through catalytic reduction of H 2 O 2 on metal catalyst thin film patterns. Si beneath the metal is etched through a redox reaction where h + are involved. This work investigated a fundamental electrochemical process during MaCE: the transport of h + , and revealed its unique correlation with the 3D profile of the etching results. It is discovered that under the uniform etching condition, etching occurs both in the Si beneath the catalysts as well as on the sidewall of the etched space. On N-type Si, the sidewall etching is intrinsically depressed, and highly vertical HAR structures are formed; on P-type Si and undoped Si, the sidewall tapering becomes significant as the pattern number and density increase. The variation of the 3D profile can be explained by the CT during etching using a Schottky junction model, which show dependence on the intrinsic properties of the Si. CT involved in the two etching process can further be correlated by diffusion or drift of h + , which explains the influence of catalysts geometry. Fabrication of micro-and nanostructures on silicon (Si) is a key step in manufacturing of modern electronic and optoelectronic devices. Especially, the high-aspect-ratio (HAR) structures, of which the vertical dimension is much larger than the lateral dimension, enable orders-of-magnitude higher integration density and superior system performance compared to that of traditional planar structures by utilizing the space inside Si. HAR structures, such as deep trenches and deep holes, have been widely used in advanced Si-based devices. For example, deep trenches are the core structures in the microelectromechanical systems; 1 deep holes serve as the interconnect routes in the emerging 3D integration technology in microelectronic packaging. 2Most of these HAR structures are fabricated by selective removal of certain volume of Si from the bulk Si substrate, which is generally referred to as the etching of Si. Until now, the major applicable Si etching method for HAR structures fabrication is the deep reactive ion etching (DRIE). 3,4 In DRIE, Si is put in a gas chamber and etched by plasma. Although DRIE is able to fabricate a wide range of HAR structures, it is suffered from high cost. On the other hand, metal-assisted chemical etching (MaCE), a novel low-cost wet chemical etching method, has attracted attention from both academia and industry.

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Section: Resultsmentioning

confidence: 99%

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confidence: 99%

Charge Transport in Uniform Metal-Assisted Chemical Etching for 3D High-Aspect-Ratio Micro- and Nanofabrication on Silicon

Zhao

Wong

2015

ECS J. Solid State Sci. Technol.

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“…An attractive feature of this process is the high density 3-D vias. The dimensions of these vias are 1.75 Â 1.75 "m, much smaller than the size of the through silicon vias in many existing 3-D technologies [24], [25].…”

Section: Synchronization In 3-d Circuitsmentioning

confidence: 99%

“…Placing the circuit blocks on adjacent planes can often produce a line with the shortest wirelength to connect these blocks. An exception is the case of small blocks within an SiP where the length of the interplane vias is greater than 100 "m [24], [74]. Placement methodologies have also been discussed where other objectives, such as thermal gradients among the physical planes and the temperature of the planes [75], are considered.…”

Section: Placement For 3-d Circuitsmentioning

confidence: 99%

“…The number of package pins also limits the clock signal and power supply networks. Additional primary challenges in 3-D circuits include the development of methodologies at the front end of the design process [21], [22], multiplane functional testing [23], thermal management techniques [68], and maturing manufacturing technologies [24]- [28].…”

Section: Introductionmentioning

confidence: 99%

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Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

2009

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Three-Dimensional Integration: A More Than Moore Technology

Pangracious

Marrakchi²,

Mehrez

2015

Lecture Notes in Electrical Engineering

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Three-dimensional integrated circuits (3D-ICs), which contain multiple layers of active devices, have the potential to dramatically enhance chip performance, functionality, and device packing density. They also provide for microchip architecture and may facilitate the integration of heterogeneous materials, devices, and signals and offer a promising solution for reducing both silicon footprint and interconnect length without shrinking the transistors. However, before these advantages can be realized, key technology and CAD challenges of 3D-ICs must be addressed. More specifically, the process required to build circuits with multiple layers of active devices and CAD tools used for design and validation of such circuits. Several such methodologies and CAD tools associated with the design fabrication of 3-D ICs are discussed in this chapter. Few successful 3D-IC design methods and CAD tools and benefits of applying 3D design to the future reconfigurable systems are also discussed in this chapter. IntroductionThe ongoing demand for greater functionality resulting in multiple IC products, longer off-chip interconnects ravage the performance of microelectronic systems. The advent of System-on-Chip (SoC) in the mid 1990s primarily addressed the increasing delay of the off-chip interconnects. Integrating all of the components on a monolithic substrate enhances the overall speed of the system, while decreasing the power consumption. To assimilate disparate technologies, however several difficulties must be surmounted to achieve high yield for the entire system. Additional system requirements for the radio frequency (RF) circuitry, passive elements, and discrete components, such us decoupling capacitors, which are not easily integrated due to performance degradation or size limitations. While Moore's law [1] and the pursuit of ever increasing transistor counts is well known in IC design and manufacturing circles, what is seldom brought to light for others, are the escalating cost and technology challenges associated with this pursuit. Smaller transistors and larger dies have been reasonable answer to this quest in the past. Stacked dies using wire bond connections and flip-chips have even been employed to create system-in-package (SiP) solutions that meet the needs of some. Looking for alternative solutions for next generation designs, that meet the performance, integration, form-factor, manufacturability, and cost requirements, may have begun to look at going up rather than out. With this trend, the Three-dimensional (3D) integration using through-silicon via (TSV) technology has gained much attention. Once the domain of specialist applications, more mainstream users, such as memories, microprocessors ans specialized logic designs are now being considered as TSV candidates. The advantages of 3D-IC integration are better electrical performance, low power consumption, lower area and weight and high performance (Fig. 2.1). Opportunities for Three-Dimensional IntegrationPerformance requirements such as increased band...

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Fabrication and Electrical Characterization of 3D Vertical Interconnects

Cited by 27 publications

References 5 publications

Charge Transport in Uniform Metal-Assisted Chemical Etching for 3D High-Aspect-Ratio Micro- and Nanofabrication on Silicon

Charge Transport in Uniform Metal-Assisted Chemical Etching for 3D High-Aspect-Ratio Micro- and Nanofabrication on Silicon

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Three-Dimensional Integration: A More Than Moore Technology

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