Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

Abbaspour, Reza; Brown, Devin K.; Bakir, Muhannad S.

doi:10.1088/1361-6439/aa544c

Cited by 25 publications

(8 citation statements)

References 39 publications

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“…The schematic cross-sectional view shown in Fig. 1 illustrates the potential TSV applications, namely (i) highlyscaled, tight-pitched TSVs for memory stacking, where the TSVs are employed for signal transmission, [15][16][17][18] (ii) finepitch TSVs for interposer applications, where the TSVs are used either as power/ground lines or to integrate the 3Dmemory stack to the other functional dies, [19][20][21][22] and (iii) coarse TSVs, which mainly used for packaging. [23][24][25] Since the demand for TSV product is ever increasing owing to their deployment in both LSI integration as well packaging purposes, it is immense to enhance the throughput of TSV fabrication in a less expensive manner.…”

Section: Introductionmentioning

confidence: 99%

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Murugesan¹,

Mori²,

Bea³

et al. 2020

Jpn. J. Appl. Phys.

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A feasibility study has been carried out to find an alternative method to the laborious cum expensive physical vapor deposition (PVD)/atomic layer deposition for the deposition of barrier and seed metal layers inside the deep Si trenches with aspect ratio (AR) greater than 10, by using low-cost, highly-scalable, CMOS-compatible electroless (EL) plating method to plate Ni as (barrier cum) seed layer for the fabrication of sub-μm as well as 10 μm width copper through-silicon-vias (Cu-TSVs). Micro-structural data revealed that both sub-μm and 10 μm width TSVs with AR ranging from 12 to 17 were completely filled with Cu by using EL-Ni as a seed layer. Further, both scanning electron microscope and energy dispersive X-ray analyzes data confirms the conformal formation of EL-Ni all through TSV sidewall and TSV bottom, which is otherwise difficult to realize by the even sophisticated PVD tool. Therefore, the EL plating method appears to be a highly promising method for the conformal formation of barrier/seed layers inside the high AR TSVs for future three-dimensional integration and packaging applications.

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Section: Introductionmentioning

confidence: 99%

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Murugesan¹,

Mori²,

Bea³

et al. 2020

Jpn. J. Appl. Phys.

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“…Resistance to electromigration can also be improved by moving to narrower TSVs as smaller stress gradients result . These drivers have resulted in the development of technology to achieve Cu‐plated TSVs with diameters of <1 μm and aspect ratios exceeding 15, although typical TSV diameters for global interconnects are more likely to be in the range of 2 to 4 μm between 2015 and 2018 with aspect ratios of 12 to 15…”

Section: Introductionmentioning

confidence: 99%

Challenges facing copper‐plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development

Lennon

Colwell

Rodbell

2018

Progress in Photovoltaics

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Copper‐plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research to demonstrate that use of Cu would not impact device reliability. However, although Cu‐plated metallisation promises significantly reduced costs for Si photovoltaics, its adoption in manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu‐plated metallisation for Si photovoltaics. These include the following: (1) increased carrier recombination due to the use of Cu for metal contact formation; (2) reduced module reliability due to adhesion or contact integrity failures; and (3) limited availability of cost‐effective processes and equipment for metal plating. For integrated circuits, Cu's low electrical resistance and high resistance to electromigration provided an impetus for the large investment in process development that was required to realise Cu‐plated interconnects. However, the technical advantages of using Cu for Si solar cell contacts are not as compelling, as solar cells can tolerate larger feature sizes thus reducing the criticality of the contact metal's conductivity and electromigration properties. Additionally, for Si photovoltaics, low cost is paramount, and new challenges arise from the need for modules to absorb light and operate in the field for 25+ years in diverse outdoor climates. However, with the scale of Si photovoltaic manufacturing expected to increase dramatically in the next decade, the use of large quantities of silver for cell metallisation will provide an incentive to address reliability concerns regarding the use of Cu for Si photovoltaic metallisation.

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“…[16][17][18][19] Furthermore, extremely small or new structures of TSVs to improve signal integrity as well as residual stress are also proposed. [20][21][22][23][24] In this research, we focus on TSV-TSV or TSV-circuitry crosstalk, as illustrated in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

Araga¹,

Kikuchi²,

Aoyagi³

2018

Jpn. J. Appl. Phys.

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Substrate noise from a single through-silicon via (TSV) and the noise attenuation by a substrate tap and a guard ring are clarified. A CMOS test vehicle is designed, and 6-µm-diameter TSVs are manufactured on a 20-µm-thick silicon substrate by the via-last method. An on-chip waveformcapturing circuitry is embedded in the test vehicle to capture transient waveforms of substrate noise. The embedded waveform-capturing circuitry demonstrates small and local noise propagation. Experimental results show increased substrate noise level induced by TSVs and the effectiveness of the substrate tap and guard ring for mitigating the crosstalk among TSVs. An analytical model to explain substrate noise propagation is developed to validate experimental results. Results obtained using the substrate model with a multilayer mesh shows good consistency with experimental results, indicating that the model can be used for examination of noise suppression methods.

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Fabrication and electrical characterization of sub-micron diameter through-silicon via for heterogeneous three-dimensional integrated circuits

Cited by 25 publications

References 39 publications

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

High aspect ratio through-silicon-via formation by using low-cost electroless-Ni as barrier and seed layers for 3D-LSI integration and packaging applications

Challenges facing copper‐plated metallisation for silicon photovoltaics: Insights from integrated circuit technology development

Evaluation of substrate noise suppression method to mitigate crosstalk among trough-silicon vias

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