Fabrication cost analysis for 2D, 2.5D, and 3D IC designs

Zhang, Chao; Sun, Guangyu

doi:10.1109/3dic.2012.6263032

Cited by 18 publications

(9 citation statements)

References 7 publications

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“…[1][2][3][4][5][7][8][9] The time frame of bonding is highly dependent on the elements of alloying system and the treatment conditions. [6] In other words, the phase diagram together with the kinetic parameters and cost considerations [10] are the keys to select the proper components of the joint material. While the initial heating of the solder until the melting point can take less than a minute to about an hour depending on the manufacturing considerations of the ICs, the melting of the interlayer can happen within a few seconds.…”

Section: Introductionmentioning

confidence: 99%

Phase Field Modeling of Joint Formation During Isothermal Solidification in 3DIC Micro Packaging

Attari

Arróyave

2016

J. Phase Equilib. Diffus.

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In this paper, a computational multi-phase field approach is utilized to study the formation of the Cu/Sn/Cu micro-joint in 3-Dimensional Integrated Circuits (3DICs). The method considers the evolution of the system during isothermal solidification at 250°C for the case of two different interlayer thicknesses (5 and 10 lm). The Cu/Sn/Cu interconnection structure is important for the micro packaging in the 3DIC systems. The thermodynamics and kinetics of growth of gCu 6 Sn 5 and e-Cu 3 Sn interfacial intermetallics (IMCs) are investigated by coupling the multiphase field method with CALPHAD approach. The interaction of the phases is addressed by assuming a metastable condition for the Cu/Sn reacting system. The simulations start with the nucleation and rapid growth of the g-Cu 6 Sn 5 IMCs at the initial stage, the nucleation and growth of e-Cu 3 Sn IMCs at the intermediate stage ending with the full consumption of Sn layer and the domination of e-Cu 3 Sn IMCs at the later stages. In addition, comparing different diffusion rates through the grain boundary of g phases show that their morphology is the direct consequence of balance of kinetic forces. This work provides a valuable understanding of the dominant mechanisms for mass transport in the Cu/Sn/Cu low volume interconnections. The results show that the phase field modeling is successful in addressing the morphological evolution and growth of IMC layers in the 3DIC joint formation.

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Section: Introductionmentioning

confidence: 99%

Phase Field Modeling of Joint Formation During Isothermal Solidification in 3DIC Micro Packaging

Attari

Arróyave

2016

J. Phase Equilib. Diffus.

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“…Interposer stacks are a widely accepted, cost-efficient alternative to 3D ICs [8], [16], [17], [18], [19], [20], [21], [22]. Here, active dies are arranged in lateral direction on a substrate-possibly on both of its sides-instead of stacking them strictly vertically.…”

Section: Interposer Stacksmentioning

confidence: 99%

“…This greatly lowers the overall manufacturing cost and also helps to improve the power efficiency. Further, interposer allow for better heat dissipation [17], [50]. In short, interposer are considered as the platform for "new multi-chip modules (MCMs)" [51], [52], with low cost, high yield, and the combination of heterogeneous integrated circuits in one package cited as the major advantages.…”

Section: Interposer Stacksmentioning

confidence: 99%

“…A key observation is that most challenges can be eased once system-level 3D integration (of 2D chips) is pursued. The related concept of interposer-based 3D integration is widely accepted nowadays [8], [16], [17], [18], [19], [20], [21], [22]; it is a practical, flexible, and cost-effective alternative to the previously more anticipated full-custom and native 3D integration.…”

Section: Introductionmentioning

confidence: 99%

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Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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“…Most of them have focused on cost modeling for 3D manufacturing (as in [5] and [6]), stacking and integration (as in [7], [8] and [9]), TSV count and die area (as in [10] and [11]). However, limited work is published on test cost modeling and its impact on the overall chip quality and cost.…”

mentioning

confidence: 99%

Quality versus cost analysis for 3D Stacked ICs

Taouil

Hamdioui

Marinissen

2014

2014 IEEE 32nd VLSI Test Symposium (VTS)

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To fulfill customer demands, IC products must satisfy the required quality generally expressed in defective parts per million (DPPM). To meet this DPPM target, appropriate test infrastructures and test approaches must be developed. This is a challenging task for 3D Stacked-ICs (3D-SIC) due to a large test flow space; each test flow may require different design-fortest features and impact the product quality and total stack cost differently. Therefore, appropriate models to predict the impact of test flows on the product quality and overall stack cost at early design stage is important for quality versus cost trade-offs. This paper presents a model that predicts the 3D product quality in terms of DPPM for different test flows and associated cost; it incorporates the quality of the wafer manufacturing, stacking and packaging process. For example, the presented case study showed that maintaining the same product quality for larger stack size might result in a significant test cost increase.

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Fabrication cost analysis for 2D, 2.5D, and 3D IC designs

Cited by 18 publications

References 7 publications

Phase Field Modeling of Joint Formation During Isothermal Solidification in 3DIC Micro Packaging

Phase Field Modeling of Joint Formation During Isothermal Solidification in 3DIC Micro Packaging

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Quality versus cost analysis for 3D Stacked ICs

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