Fabrication of epitaxial CoSi2 nanowires

Kluth, Patrick; Zhao, Qing‐Tai; Winnerl, Stephan; Lenk, St.; Mantl, S.

doi:10.1063/1.1390318

Cited by 18 publications

(18 citation statements)

References 7 publications

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“…Nevertheless, nanostructuring is still a challenge and different approaches are followed [1,2]. Recently, nanowires have attracted a lot of interest because they are required to interconnect functional units in nano-and molecular electronics [3,4]. Nanowires smaller than the ones fabricated thus far are desirable.…”

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confidence: 99%

Nanowires and Nanorings at the Atomic Level

et al. 2003

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The step-flow growth mode is used to fabricate Si and Ge nanowires with a width of 3.5 nm and a thickness of one atomic layer (0.3 nm) by self-assembly. Alternating deposition of Ge and Si results in the formation of a nanowire superlattice covering the whole surface. One atomic layer of Bi terminating the surface is used to distinguish between the elements Si and Ge. A difference in apparent height is measured in scanning tunneling microscopy images for Si and Ge. Also, different kinds of twodimensional Si=Ge nanostructures like alternating Si and Ge nanorings having a width of 5-10 nm were grown.

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mentioning

confidence: 99%

Nanowires and Nanorings at the Atomic Level

et al. 2003

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“…특히, 원자 수 개의 크기를 가지는 소자에 관한 연구는 최근 나노 과 학 기술의 핵심으로 주목을 받고 있다. 1,2) 현재 식각 공 정을 통해 제작할 수 있는 소자의 폭은 최소 수십 nm 정도이지만, Si 표면에 금속의 자발적인 반응을 이용하 면 폭 10 nm 이하의 나노선을 성장시킬 수 있다. 이렇 게 성장된 금속 나노선은 다이오드, 트랜지스터 등과 이 들을 조합한 기본 논리연산회로, SRAM, DRAM 등에 구현될 수 있다.…”

Section: 서 론unclassified

Indium Nanowire Growth on Si (001) Surface Using Density Functional Theory

Kim¹,

Kim²,

Seo³

et al. 2009

Korean. J. Mater. Res.

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Density functional theory was utilized to investigate the growth of an indium nanowire on a Si (001) buckled surface. A site between the edge of two Si dimers is most favorable when the first In atom is adsorbed on the surface at an adsorption energy level of 2.26 eV. The energy barriers for migration from other sites to the most favorable site are low. When the second In atom is adsorbed next to the first In atom to form an In dimer perpendicular to the Si dimer row, the adsorption energy is the highest among all adsorption sites. The third In atom prefers either of the sites next to the In dimer along the In dimer direction. The fourth In atom exhibited the same tendency showed by the second atom. The second and fourth In adsorption energy levels are higher than the first and third levels as the In atoms consume the third valence electron by forming In dimers. Therefore, the In nanowire grows perpendicular to the Si dimer row on the Si (001) surface, as it satisfies the bonding of the three valence electrons of the In atoms.

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“…This technique is based on local oxidation of silicide (LOCOSI) layers. The 50-nm gaps in CoSi 2 layers, 2 as well as the 50-nm CoSi 2 wires, 3 have been generated. The sub-100-nm Schottky barrier (SB) MOSFETs have been successfully fabricated using those structures.…”

Section: Introductionmentioning

confidence: 99%

Nanopatterning of epitaxial CoSi2 using oxidation in a local stress field and fabrication of nanometer metal-oxide-semiconductor field-effect transistors

Zhao¹,

Kluth²,

Bay³

et al. 2004

Journal of Applied Physics

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A patterning method for the generation of epitaxial CoSi 2 nanostructures was developed based on anisotropic diffusion of Co/ Si atoms in a stress field during rapid thermal oxidation (RTO). The stress field is generated along the edge of a mask consisting of a thin SiO 2 layer and a Si 3 N 4 layer. During RTO of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. The technique was used to make 50-nm channel-length metal-oxide-semiconductor field-effect transistors (MOSFETs). These highly uniform gaps define the channel region of the fabricated device. Two types of MOSFETs have been fabricated: symmetric transistor structures, using the separated silicide layers as Schottky source and drain, and asymmetric transistors, with n + source and Schottky drain. The asymmetric transistors were fabricated by an ion implantation into the unprotected CoSi 2 layer and a subsequent out diffusion to form the n + source. The detailed fabrication process as well as the I-V characteristics of both the symmetric and asymmetric transistor structures will be presented.

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Fabrication of epitaxial CoSi2 nanowires

Abstract: Nanopatterning of epitaxial Co Si 2 using oxidation in a local stress field and fabrication of nanometer metaloxide-semiconductor field-effect transistors

Cited by 18 publications

References 7 publications

Nanowires and Nanorings at the Atomic Level

Nanowires and Nanorings at the Atomic Level

Indium Nanowire Growth on Si (001) Surface Using Density Functional Theory

Nanopatterning of epitaxial CoSi2 using oxidation in a local stress field and fabrication of nanometer metal-oxide-semiconductor field-effect transistors

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