Nanopatterning of epitaxial CoSi2 using oxidation in a local stress field and fabrication of nanometer metal-oxide-semiconductor field-effect transistors

Abstract

A patterning method for the generation of epitaxial CoSi 2 nanostructures was developed based on anisotropic diffusion of Co/ Si atoms in a stress field during rapid thermal oxidation (RTO). The stress field is generated along the edge of a mask consisting of a thin SiO 2 layer and a Si 3 N 4 layer. During RTO of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. The technique was used to make 50-nm channel-length metal-oxide-semiconductor field-effect transistors (MOSFETs). These highly uniform gaps define the channel region of the fabricated device. Two types of MOSFETs have been fabricated: symmetric transistor structures, using the separated silicide layers as Schottky source and drain, and asymmetric transistors, with n + source and Schottky drain. The asymmetric transistors were fabricated by an ion implantation into the unprotected CoSi 2 layer and a subsequent out diffusion to form the n + source. The detailed fabrication process as well as the I-V characteristics of both the symmetric and asymmetric transistor structures will be presented.

Tailoring of epitaxial CoSi2/Si nanostructures by low temperature wet oxidation

“…An initially 60 nm wide separation between two silicide layers has been effectively reduced to sub-20 nm dimensions and further oxidation caused merging of the two layers. As one application, such structures could be useful to reduce the channel length in ultra-short channel Schottky barrier MOSFETs similar to the ones presented in [10]. They also may be utilized as nano-contacts such as break junctions for research purposes.…”

“…Gaps with dimensions down to 40 nm and silicide wires with diameters down to 50 nm were generated in 20-30 nm thick epitaxial CoSi 2 layers on conventional and SOI substrates [5][6][7]. The resulting nanostructures have been used for fabrication of 50 nm short channel Schottky barrier MOSFETs [8][9][10].…”