Fabrication of MOS-integrated metallic single electron memories

Abstract

The fabrication of a lateral single electron memory (LSEM) based on the integration of a metallic multiple tunnel junction (MTJ) and a memory node (MN) on a Si metal oxide semiconductor field effect transistor (MOS) has been investigated. High resolution electron beam lithography (HREBL) was used to fabricate devices presenting good morphological characteristics. The MN can be made as narrow as 50 nm, with an MTJ comprising a 5x5 array of sub-5 nm Au islands deposited by thermal evaporation, and implemented on a short 0.5 gm channel MOS. An operating temperature close to 77 K with the two memory levels relying on the excess or shortfall of approximately 30 electrons is expected.

(Invited) Temperature Influence on Current Leakage and Hysteresis of Nc-CdSe Embedded Zr-Doped HfO2 High-k Dielectric Nonvolatile Memory

“…The NDR peak is commonly observed in nanocrystals embedded dielectrics (14,15,17). The NDR peak is not detected at the high temperature because it is difficult to retain the high energy electrons (19,20). Previously, it was reported that the leakage current of the control sample, i.e., with the ZrHfO high-k gate dielectric without any embedded layers, followed two different mechanisms in the negative V g region, i.e., Schottky emission (SE) at the low electric field and Poole-Frenkel (P-F) mechanism at the high electric field (21).…”