Fabrication of nanoimprint template in Si with high etch rate by non-switch DRIE process

Wang, Xudi; Chen, Yifang; Cui, Zheng

doi:10.1016/j.mee.2008.01.073

Cited by 13 publications

(10 citation statements)

References 8 publications

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“…A similar trend has been reported for silicon nanolines (although an order of magnitude greater in dimension) whereby a ratio of 5:2 C 4 F 8 :SF 6 resulted in anisotropic etching and ratios close to 1:1 C 4 F 8 :SF 6 lead to isotropic etching and destruction of the patterns. 26 Prolonged etching beyond 60 nm was limited by the 15 nm polystyrene film as the PS line is extremely thin after 60 s of silicon etching. Overall, aspect ratios of 3:1 (61 nm deep and 18 nm wide) could be created in the underlying silicon substrate with a negligible loss in critical dimension (∼3 nm) by employing TEM techniques to first establish the end point of the PMMA removal step.…”

Section: Resultsmentioning

confidence: 99%

Monitoring PMMA Elimination by Reactive Ion Etching from a Lamellar PS-b-PMMA Thin Film by ex Situ TEM Methods

Farrell

Petkov²,

Shaw

et al. 2010

Macromolecules

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Block copolymer thin films require selective elimination of one of their constituent blocks to access their potential as lithographic nanopatterns. This paper demonstrates an on-substrate TEM-based approach for establishing the removal of poly(methyl methyacrylate) from vertically oriented lamellar polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) thin films and subsequent transfer to the underlying silicon by reactive ion etching. The ex situ microscopy technique presents an insight into the removal of PMMA, the etch end point, PS faceting, etch anisotropy, and residual PS thickness.

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Section: Resultsmentioning

confidence: 99%

Monitoring PMMA Elimination by Reactive Ion Etching from a Lamellar PS-b-PMMA Thin Film by ex Situ TEM Methods

Farrell

Petkov²,

Shaw

et al. 2010

Macromolecules

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“…To fabricate micro porous silicon template, the combined process of UV lithography and ICP etching were employed [30]. Firstly, the silicon wafer was spin coated using photoresist (BP212) and softly baked under 110°C for 1 min on a Spin Coater (CEE model 100CB, Brewer Science Co., USA).…”

Section: Preparation Of Micro Porous Silicon Templatementioning

confidence: 99%

“…Results and discussion 3.1. PS micro/nano pillars-aligned patterns The microporous silicon templates were fabricated by combined process of UV lithography and ICP etching [30], and the nanoporous anodic alumina templates were prepared by the so-called two-step anodic oxidation [31,32]. Their SEM top-view images are presented in Figure 1.…”

Section: Characterization and Measurementmentioning

confidence: 99%

Wettability transition of plasma-treated polystyrene micro/nano pillars-aligned patterns

Kong¹,

Yung²,

Xu³

et al. 2010

Express Polym. Lett.

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Abstract. This paper reports the wettability transition of plasma-treated polystyrene (PS) micro/nano pillars-aligned patterns. The micro/nano pillars were prepared using hot embossing on silicon microporous template and alumina nanoporous template, which were fabricated by ultraviolet (UV) lithography and inductive coupled plasma (ICP) etching, and two-step anodic oxidation, respectively. The results indicate that the combination of micro/nano patterning and plasma irradiation can easily regulate wettabilities of PS surfaces, i.e. from hydrophilicity to hydrophobicity, or from hydrophobicity to superhydrophilicity. During the wettability transition from hydrophobicity to hydrophilicity there is only mild hydrophilicity loss. After plasma irradiation, moreover, the wettability of PS micro/nano pillars-aligned patterns is more stable than that of flat PS surfaces. The observed wettability transition and wettability stability of PS micro/nano pillars-aligned patterns are new phenomena, which may have potential in creating programmable functional polymer surfaces.

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“…Therefore, a tilt angle of the side wall is generated in DRIE process. In recent years, many studies have already been performed to realise a small tilt angle of microstructure via adjusting DRIE operational parameters, including etch cycle time, passivation cycle time, platen power, coil power, temperature of substrate cooling, and chamber pressure [8][9][10][11]. However, they involve a large number of experiments to optimise DRIE process recipes for specific structure.…”

Section: Introductionmentioning

confidence: 99%

High‐accuracy silicon‐on‐insulator accelerometer with an increased yield rate

Shen

et al. 2015

Micro & Nano Letters

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This Letter presents a high accuracy silicon-on-insulator (SOI) capacitive accelerometer using a backside dry release process. To increase the yield rate of the process, the deep reactive iron etching (DRIE) process was improved using a grooved accompany wafer to balance the pressure inside the back cavity of the SOI devices. By using this method, almost all the devices after the DRIE will not crack. Thus, the yield rate is significantly increased. Furthermore, the DRIE process was improved by dividing the DRIE process into four stages to decrease the tilt angle of DRIE. It is experimentally demonstrated that the tilt angle of the side wall was decreased from 0.81°to 0.27°and the loss of the capacitive sensitivity caused by the error was decreased from 28 to 8%. Test results show that sensitivity, bias stability, and noise floor of the accelerometer is 3.1 V/g, 16 μg, and 3.1 μg/√Hz, respectively.

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Fabrication of nanoimprint template in Si with high etch rate by non-switch DRIE process

Cited by 13 publications

References 8 publications

Monitoring PMMA Elimination by Reactive Ion Etching from a Lamellar PS-b-PMMA Thin Film by ex Situ TEM Methods

Monitoring PMMA Elimination by Reactive Ion Etching from a Lamellar PS-b-PMMA Thin Film by ex Situ TEM Methods

Wettability transition of plasma-treated polystyrene micro/nano pillars-aligned patterns

High‐accuracy silicon‐on‐insulator accelerometer with an increased yield rate

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