Fabrication of normally-off GaN nanowire gate-all-around FET with top-down approach

Abstract

Lateral GaN nanowire gate-all-around transistor has been fabricated with top-down process and characterized. A triangle-shaped GaN nanowire with 56 nm width was implemented on the GaN-on-insulator (GaNOI) wafer by utilizing (i) buried oxide as sacrificial layer and (ii) anisotropic lateral wet etching of GaN in tetramethylammonium hydroxide solution. During subsequent GaN and AlGaN epitaxy of source/drain planar regions, no growth occurred on the nanowire, due to self-limiting growth property. Transmission electron microscopy and energy-dispersive X-ray spectroscopy elemental mapping reveal that the GaN nanowire consists of only Ga and N atoms. The transistor exhibits normally-off operation with the threshold voltage of 3.5 V and promising performance: the maximum drain current of 0.11 mA, the maximum transconductance of 0.04 mS, the record off-state leakage current of ∼10−13 A/mm, and a very high Ion/Ioff ratio of 108. The proposed top-down device concept using the GaNOI wafer enables the fabrication of multiple parallel nanowires with positive threshold voltage and is advantageous compared with the bottom-up approach.

Review of GaN Nanostructured Based Devices

“…The SEM image of GaN/AlGaN nanowires on Si is shown in Figure 23 [99]. The lateral GaN nanowire gate all around transistor with top down process has been fabricated and characterized by Im et al [100]. A triangle shaped GaN nanowire with 56 nm width was implemented on the GaN-on-insulator (GaNOI) wafer by utilizing buried oxide as sacrificial layer and anisotropic lateral wet etching of GaN in tetramethylammonium hydroxide solution [100].…”

“…The lateral GaN nanowire gate all around transistor with top down process has been fabricated and characterized by Im et al [100]. A triangle shaped GaN nanowire with 56 nm width was implemented on the GaN-on-insulator (GaNOI) wafer by utilizing buried oxide as sacrificial layer and anisotropic lateral wet etching of GaN in tetramethylammonium hydroxide solution [100]. During the subsequent GaN and AlGaN epitaxy of source/drain planar regions, no growth occurred on the nanowire, due to self-limiting growth property.…”

“…These attractive on/off state characteristics are the full depletion result of the GAA (gate all around) nanowire, without the parasitic influence of GaN buffer layer. The GaN nanowire GAA transistor is very promising for nanoscale integrated CMOS circuits and high performance/high power application [100]. Figure 24 shows the schematic illustration of the of GaN nanowire GAA transistor fabrication sequence of a GaN nanowire GAA transistor.…”

“…The schematic illustration of the of a GaN nanowire GAA transistor is shown Figure 24 (a). The structure of GaNOI wafer, prepared by smart cut technology is shown in Figure 24 (b) [100]. The formation of GaN nanowire arrays is shown in Figure 24 (c).…”

“…The release of GaN nanowire arrays by removing the sacrificial SiO2 buried oxide is shown in Figure 24 (e). The regrowth of AlGaN/GaN heterostructure on the patterned GaNOI wafer is shown in Figure 24 (f) [100]. …”