Lateral GaN nanowire gate-all-around transistor has been fabricated with top-down process and characterized. A triangle-shaped GaN nanowire with 56 nm width was implemented on the GaN-on-insulator (GaNOI) wafer by utilizing (i) buried oxide as sacrificial layer and (ii) anisotropic lateral wet etching of GaN in tetramethylammonium hydroxide solution. During subsequent GaN and AlGaN epitaxy of source/drain planar regions, no growth occurred on the nanowire, due to self-limiting growth property. Transmission electron microscopy and energy-dispersive X-ray spectroscopy elemental mapping reveal that the GaN nanowire consists of only Ga and N atoms. The transistor exhibits normally-off operation with the threshold voltage of 3.5 V and promising performance: the maximum drain current of 0.11 mA, the maximum transconductance of 0.04 mS, the record off-state leakage current of ∼10−13 A/mm, and a very high Ion/Ioff ratio of 108. The proposed top-down device concept using the GaNOI wafer enables the fabrication of multiple parallel nanowires with positive threshold voltage and is advantageous compared with the bottom-up approach.

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Over the past decade the interest in gallium nitride – based electronic applications increased significantly. The economical advantages of GaN-based applications imposed the development of new manufacturing technologies. Among them, wafer bonding process solutions could be further developed and optimized for the manufacturing of GaN engineered substrates. The most significant benefit of using wafer bonding for GaN-based applications is the possibility to combine GaN with various substrate materials, offering a high flexibility by imposing strict quality requirements only to the surfaces of the substrates and not to their crystal structure.This work proposes two different process flows for “GaN-on-Something” substrates manufacturing. The features and benefits of the two process flows are illustrated by experimental results.

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