Fabrication of $\Omega$ -gated Negative Capacitance FinFETs and SRAM

Sung, Po-Jung; Su, Chun-Jung; Lu, Darsen D.; Luo, Shien-Chun; Kao, K.-H.; Ciou, Jhang-Yan; Jao, Che-Yu; Hsu, Hui-Shun; Wang, C.-J.; Hong, Tzu-Chieh; Liao, Tzu-Han; Fang, Chih-Cheng; Wang, Yi-Sheng; Huang, Hao; Li, J.-H.; Huang, Yu‐Ching; Hsueh, Fu Kuo; Wu, Chien-Ting; C.-Y., W.; Huang, Kun-Ping; Lee, Y.-J.; Chao, Tien−Sheng; Li, J.-Y.; Wu, Wen−Fa; Yeh, Wen–Kuan; Wang, Y.-H.

doi:10.1109/vlsi-tsa.2019.8804663

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…Fig. 2 shows the P-V characteristics of planar ferroelectric capacitors measured at the different process steps to examine the effect of the thermal budget on the ferroelectricity [15]. The area under the gate electrode is 2500 mm 2 , and the period time of the P-V loop is 1 ms.…”

Section: Results and Discussion A Effect Of Fga On Fefetsmentioning

confidence: 99%

“…Fabrication of the FeFET [15]: Initially, the Si layer of a ptype SOI wafer was thinned down to 20 nm. The active region was defined by e-beam lithography and dry etching processes.…”

Section: Device Fabricationmentioning

confidence: 99%

“…According to works of literature, FeFETs with a broad channel width often show SS below 60 mV/dec is over two orders of magnitude of I D [10]- [14]. However, as a ferroelectric material is applied to nanoscale structures, such as FinFET or nanowire, SS below 60 mV/dec is often under two orders of magnitude of I D [6]- [7], [15]- [18]. Therefore, a channel dimension may influence on electrical characteristics of FeFETs, resulting in ultra-steep SS.…”

Section: Introductionmentioning

confidence: 99%

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Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Sung

et al. 2020

IEEE J. Electron Devices Soc.

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In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counterclockwise (CCW) loops. INDEX TERMS FeFET, forming gas annealing (FGA), steep slop, HfZrO 2 , ferroelectric.

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Section: Results and Discussion A Effect Of Fga On Fefetsmentioning

confidence: 99%

“…Fabrication of the FeFET [15]: Initially, the Si layer of a ptype SOI wafer was thinned down to 20 nm. The active region was defined by e-beam lithography and dry etching processes.…”

Section: Device Fabricationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Sung

et al. 2020

IEEE J. Electron Devices Soc.

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“…Ion implantation for source and drain formation was performed separately for n-type (nFET) and p-type (pFET) devices. Dopant activation was accomplished through microwave annealing, which, according to our previous study, does not affect Fe properties [17]. The final device crosssectional transmission electron microscopy image is displayed in figure 1.…”

Section: Device Fabrication and Measurementsmentioning

confidence: 99%

Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks

Lu¹,

Baig

et al. 2020

Semicond. Sci. Technol.

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In this paper, a compact drain current formulation that is simple and adequately computationally efficient for the simulation of neural network online training was developed for the ferroelectric memory transistor. Tri-gate ferroelectric field-effect transistors (FETs) with Hf 0.5 Zr 0.5 O 2 gate insulators were fabricated with a gate-first high-k metal gate CMOS process. Ferroelectric switching was confirmed with double sweep and pulse programming and erasure measurements. Novel characterization scheme for drain current was proposed with minimal alteration of ferroelectric state in subthreshold for accurate threshold voltage measurements. The resultant threshold voltage exhibited highly linear and symmetric across multilevel states. The proposed compact formulation accurately captured the FET gate-bias dependence by considering the effects of series resistance, Coulomb scattering, and vertical field dependent mobility degradation.

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Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs

Jin

Lee

et al. 2021

IEEE Trans. Electron Devices

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Fabrication of $\Omega$ -gated Negative Capacitance FinFETs and SRAM

Cited by 3 publications

References 3 publications

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Computationally efficient compact model for ferroelectric field-effect transistors to simulate the online training of neural networks

Study on the Roles of Charge Trapping and Fixed Charge on Subthreshold Characteristics of FeFETs

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