Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Gomez, L.; Canonico, M.; Kim, Meekyung; Hashemi, Pouya; Hoyt, Judy L.

doi:10.1007/s11664-007-0337-8

Cited by 10 publications

(7 citation statements)

References 8 publications

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“…To study the effects of bar width, these structures are patterned into nanoscale gratings of different sizes using electron-beam lithography. 6,10 The resulting structures have the same orientation as our computational models.…”

Section: Introductionmentioning

confidence: 87%

Strain relaxation in Si/Ge/Si nanoscale bars from molecular dynamics simulations

Park

Atkulga

Grama

et al. 2009

Journal of Applied Physics

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We use molecular dynamics (MD) with the reactive interatomic potential ReaxFF to characterize the local strains of epitaxial Si/Ge/Si nanoscale bars as a function of their width and height. While the longitudinal strain (along the bars length) is independent of geometry, surface relaxation leads to transverse strain relaxation in the Ge section. This strain relaxation increases with increasing height of the Ge section and reduction in its width and is complete (i.e., zero transverse strain) for roughly square cross sections of Ge leading to a uniaxial strain state. Such strain state is desirable in some microelectronics applications. From the MD results, which are in excellent agreement with experiments, we derive a simple model to predict lateral strain as a function of geometry for this class of nanobars.

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Section: Introductionmentioning

confidence: 87%

Strain relaxation in Si/Ge/Si nanoscale bars from molecular dynamics simulations

Park

Atkulga

Grama

et al. 2009

Journal of Applied Physics

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“…Although large-diameter Ge wafers are available, one may resort to strainedSi/strained-Ge heterostructure MOSFETs on bulk substrates, which can be fabricated by a bond and etch-back technique. 91 High-mobility carriers in strained-Ge channels are confined in strained-Si/ strained-Ge heterostructures with discontinuous valence bands. To deposit Ge layers as smooth, atomically flat, relaxed interfaces, Si 1Àx Ge x dislocation blocking layers can be used to fabricate high-mobility Ge-channel pMOSs.…”

Section: Germanium (Ge) Channelmentioning

confidence: 99%

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Song

Zhou

et al. 2011

Journal of Elec Materi

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The aggressive downscaling of complementary metal-oxide-semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal-oxide-semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/ drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new highmobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III-V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.

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“…In recent years several interesting approaches have been investigated to address this challenge. A direct approach is the enhancement of the carrier mobility by means of introducing strain into the Si channel (1,2). This idea has resulted in significant improvement and, hence, is now adopted into the CMOS process.…”

Section: Introductionmentioning

confidence: 99%

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

et al. 2014

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We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

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Fabrication of Strained-Si/Strained-Ge Heterostructures on Insulator

Cited by 10 publications

References 8 publications

Strain relaxation in Si/Ge/Si nanoscale bars from molecular dynamics simulations

Strain relaxation in Si/Ge/Si nanoscale bars from molecular dynamics simulations

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

Fabrication of Relaxed Germanium on Insulator via Room Temperature Wafer Bonding

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