The field effect transistors (FETs) based on thin layer MoS 2 often have large hysteresis and unstable threshold voltage in their transfer curves, mainly due to the charge trapping at the oxidesemiconductor interface. In this paper, the charge trapping and de-trapping processes at the SiO 2 -MoS 2 interface are studied. The trapping charge density and time constant at different temperatures are extracted. Making use of the trapped charges, the threshold voltage of the MoS 2 based metaloxide-semiconductor FETs is adjusted from 4 V to À45 V. Furthermore, the impact of the trapped charges on the carrier transport is evaluated. The trapped charges are suggested to give rise to the unscreened Coulomb scattering and/or the variable range hopping in the carrier transport of the MoS 2 sheet. 6-12 Besides in low power consumption electronics, devices based on MoS 2 , WS 2 , etc., also show potential for application in chemical sensing, light emitting, photo detecting, photovoltaics, and integrated flexible circuits. [13][14][15][16][17][18][19][20][21][22][23][24] Among these devices, the structure of metal-oxide-semiconductor (MOS) is mostly used. Charge trapping at the interface of the oxide and the semiconductor is common, 25,26 and MOS devices based on MoS 2 are not exceptional. 27 On one hand, charge trapping causes hysteresis and relaxation, hindering the stability of operational circuits, sensors, and photo detectors;28-30 on the other hand, charge trapping plays a key role in MoS 2 based multifunctional photoresponsive devices and flexible transparent multibit memory devices; [31][32][33][34] what is more, charge trapping offers a potential techniques for threshold voltage adjustment. 30 To better develop devices based on MoS 2 , understanding the charge trapping at the interface between the oxide and MoS 2 is necessary. SiO 2 is one of the most commonly used dielectric in MoS 2 based devices. Although trapped charges in the SiO 2 /Si substrate has been suggested to be the dominant source of potential fluctuations in MoS 2 field effect transistors (FETs), 35 there is no study on the charge trapping process for the SiO 2 in the MoS 2 based devices, and the effects of such trapped charges on the carrier transport is not clear so far. Here, the charge trapping and de-trapping processes at the MoS 2 -SiO 2 interface are studied, and their impact on the carrier transport is evaluated.MoS 2 devices were fabricated using cleaved MoS 2 sheets on SiO 2 /Si substrates (Figure 1(a)). To ensure the cleanness at the SiO 2 /MoS 2 interface, the process was done with extreme care. 36 The source and drain electrodes were patterned using electron beam lithography, followed by the deposition of Ti/ Au 5 nm/80 nm using electron beam evaporation. The heavily doped Si substrate was used as the back gate electrode. The thickness of the MoS 2 sheet is 3 nm, characterized by atomic force microscope (AFM), corresponding to three layers, as confirmed by the Raman spectrum. [36][37][38] The homogeneous contrast in the optical microscope and...