Charge trapping at the MoS2-SiO2 interface and its effects on the characteristics of MoS2 metal-oxide-semiconductor field effect transistors

Abstract

The field effect transistors (FETs) based on thin layer MoS 2 often have large hysteresis and unstable threshold voltage in their transfer curves, mainly due to the charge trapping at the oxidesemiconductor interface. In this paper, the charge trapping and de-trapping processes at the SiO 2 -MoS 2 interface are studied. The trapping charge density and time constant at different temperatures are extracted. Making use of the trapped charges, the threshold voltage of the MoS 2 based metaloxide-semiconductor FETs is adjusted from 4 V to À45 V. Furthermore, the impact of the trapped charges on the carrier transport is evaluated. The trapped charges are suggested to give rise to the unscreened Coulomb scattering and/or the variable range hopping in the carrier transport of the MoS 2 sheet. 6-12 Besides in low power consumption electronics, devices based on MoS 2 , WS 2 , etc., also show potential for application in chemical sensing, light emitting, photo detecting, photovoltaics, and integrated flexible circuits. [13][14][15][16][17][18][19][20][21][22][23][24] Among these devices, the structure of metal-oxide-semiconductor (MOS) is mostly used. Charge trapping at the interface of the oxide and the semiconductor is common, 25,26 and MOS devices based on MoS 2 are not exceptional. 27 On one hand, charge trapping causes hysteresis and relaxation, hindering the stability of operational circuits, sensors, and photo detectors;28-30 on the other hand, charge trapping plays a key role in MoS 2 based multifunctional photoresponsive devices and flexible transparent multibit memory devices; [31][32][33][34] what is more, charge trapping offers a potential techniques for threshold voltage adjustment. 30 To better develop devices based on MoS 2 , understanding the charge trapping at the interface between the oxide and MoS 2 is necessary. SiO 2 is one of the most commonly used dielectric in MoS 2 based devices. Although trapped charges in the SiO 2 /Si substrate has been suggested to be the dominant source of potential fluctuations in MoS 2 field effect transistors (FETs), 35 there is no study on the charge trapping process for the SiO 2 in the MoS 2 based devices, and the effects of such trapped charges on the carrier transport is not clear so far. Here, the charge trapping and de-trapping processes at the MoS 2 -SiO 2 interface are studied, and their impact on the carrier transport is evaluated.MoS 2 devices were fabricated using cleaved MoS 2 sheets on SiO 2 /Si substrates (Figure 1(a)). To ensure the cleanness at the SiO 2 /MoS 2 interface, the process was done with extreme care. 36 The source and drain electrodes were patterned using electron beam lithography, followed by the deposition of Ti/ Au 5 nm/80 nm using electron beam evaporation. The heavily doped Si substrate was used as the back gate electrode. The thickness of the MoS 2 sheet is 3 nm, characterized by atomic force microscope (AFM), corresponding to three layers, as confirmed by the Raman spectrum. [36][37][38] The homogeneous contrast in the optical microscope and...

Reversible hysteresis inversion in MoS2 field effect transistors

“…2d, indicating hysteresis inversion. The hysteresis direction (clockwise at room temperature 18,22,23 and anti-clockwise at high temperature 29 ) is the same as stated in earlier reports. However, the reasons given for hysteresis in these reports such as adsorbates, oxide and interface traps do not explain hysteresis inversion and its reversibility.…”

“…3 and Table 1) considered in previous studies. [16][17][18][19]22,23,25 Adsorbate mediated hysteresis mechanism 18,19 is shown in Fig. 3a.…”

“…15 Comparison of previous reports on hysteresis in MoS 2 devices with this work is listed in Table 1. Hysteresis observed in previous studies [16][17][18] has been attributed to several possibilities such as adsorption of water molecules, [18][19][20][21] oxide traps close to MoS 2 , 22 oxide-MoS 2 interface traps 23,24 and gate voltage stress effects. 25 A lack of uniformity in the hysteresis data and consensus on its origin among the reports listed in Table 1 results, at least partly, from differences in measurement conditions as well as device architecture.…”

Highly-stable black phosphorus field-effect transistors with low density of oxide traps

“…4e we compare the typical D ot extracted for our BPFETs with literature values for different technologies. [33][34][35][36][37][38][39][40] At room temperature the density of active oxide traps in our devices is~10 17 cm…”

“…1a). 13,15 The stability and reliability of all 2D transistors investigated so far is reduced by charge trapping in oxide traps [16][17][18] with very broad distributions of time constants. 19 This presents one of the main road blocks towards commercialization of 2D technologies.…”