Reversible hysteresis inversion in MoS2 field effect transistors

Abstract

The origin of threshold voltage instability with gate voltage in MoS 2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS 2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS 2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS 2 on SiO 2 . Additional hysteresis measurements on suspended (~100 nm air gap between MoS 2 and SiO 2 ) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS 2 . At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p + Si gate leads to hysteresis collapse at~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current-voltage (I-V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS 2 transistors have also been demonstrated. npj 2D Materials and Applications (2017) 1:34 ; doi:10.1038/s41699-017-0038-y INTRODUCTION Among two-dimensional materials, graphene 1,2 was the first to be isolated and studied with respect to electronic applications. Due to lack of an energy bandgap in graphene, other 2D materials such as layered transition metal dichalcogenides (TMDs) comprising a wide selection of materials with different bandstructures, and therefore different electrical and optical properties, have garnered significant attention.3-5 Molybdenum disulfide (MoS 2 ) has emerged as a prospective candidate for transistor applications. The presence of a direct bandgap (~1.8 eV) in monolayer form and an indirect bandgap (~1.2 eV) in multilayer MoS 2 makes it a promising channel material for field effect transistors (FETs).

Multimechanism Synergistic Photodetectors with Ultrabroad Spectrum Response from 375 nm to 10 µm

“…The fitting curves based on Equation (1) (Figure 3b,d) reveal adequate agreement with experimental data; moreover, we obtain τ 1 = 5.5 ms for 4 µm irradiation and τ 2 = 52.5 ms for 10 µm irradiation. [33,34] In this device, the carrier concentration in MoS 2 is completely modulated by the remanent polarization field. First, during the device fabrication, the polyimide substrate was thinned to 1.7 µm, thus producing a quasi-freestanding P(VDF-TrFE) film, and effectively reducing its heat capacitance.…”

Pressure‐Tunable Ambipolar Conduction and Hysteresis in Thin Palladium Diselenide Field Effect Transistors

“…Hysteresis has been reported in FETs based on nanotubes, graphene, and TMDCs, owing to charge transfer, charge trapping or charge polarization, although these mechanisms are still under debate. For example, in the MoS 2 ‐based FETs, charge traps may arise from the trapping centers at MoS 2 /SiO 2 interface, the adsorbates on the MoS 2 channel, or from intrinsic sulfur vacancies and other crystal defects . It is highly desirable to have a comprehensive understanding of the hysteresis and achieve a good control so that it can be either eliminated to avoid threshold voltage instability or conveniently exploited, for instance, into memory devices …”

Emerging Artificial Two-Dimensional van der Waals Heterostructures for Optoelectronics

“…The ultrathin nature makes 2D semiconductors highly suitable as the readout channel in memory, as their conductance can be modulated greatly by slight charge trapping, including by the inherent trap states in devices. In literatures, the prepared MoS 2 often exhibits midgap trap states [54], and the device also suffers from interface defect states, e.g., at the interface with SiO 2 [55], which may capture some charges under gate modulation by the shifted Fermi level E F (the trap states below E F are prone to be filled with electrons, while those states above E F tend to be empty). This usually results in large hysteresis in field-effect devices and different conduction states after positive and negative gate stress.…”