Fabrication of thick silicon dioxide layers for thermal isolation

Abstract

This paper reports a method of fabricating very thick (10-100 µm) silicon dioxide layers for thermal isolation without the need for very long deposition or oxidation. Deep reactive ion etching (DRIE) is used to create high-aspect-ratio trenches and silicon pillars, which are then oxidized and/or refilled with LPCVD oxide to create oxide layers as thick as the DRIE allows. Stiffeners are used to provide support for the pillars during oxidation. Thermal tests show that such thick silicon dioxide layers can effectively thermally isolate heated structures from neighboring structures within a distance of hundreds of microns. The thermal conductivity of the thick SiO 2 is measured to be ∼1.1 W (m K). Such SiO 2 diaphragms of thickness 50-60 µm can sustain an extrinsic shear stress up to 3-5 MPa.

Pure‐silica optical waveguides, fiber couplers, and high‐aspect ratio submicrometer channels for electrokinetic separation devices

“…All of the optical and fluidic structures were etched simultaneously using anisotropic deep-reactive ion etching (DRIE) and subsequently oxidized to form optical and fluidic channel networks. This process scheme is similar to the one recently used by Jiang et al [20] and Zhang and Najafi [21] for fabrication of thick silicon dioxide layers for thermal isolation in microelectronic components. The main difference to our previous devices, which also contained UV-transparent waveguides [22,23], is that the waveguides in this work are embedded in the bulk of the substrate and not fabricated on top of the wafer using surface micromachining techniques (e.g., plasma-enhanced chemical vapor deposition, PECVD).…”

A Temperature-Stable Piezoelectric MEMS Oscillator Using a CMOS PLL Circuit for Temperature Sensing and Oven Control

“…To build a two-resonator compensation system, both an uncompensated and a TCF-compensated resonator are fabricated on a thermally isolated platform using the MEMS process in [5], [11], and [12]. The structural layers of the resonators are composed of a 20 μm-thick single-crystalline silicon device layer and a 0.6 μm-thick AlN piezoelectric stack layer.…”

Design, fabrication and characterization of a femto-farad capacitive sensor for pico-liter liquid monitoring

“…In order to avoid a CMP process, the surface topography needs to be kept as flat as possible, so that an easy planarization process can be applied. To achieve this, both the fabrication process and the geometric sizes of the trenches need to be optimized, so that no voids between the etched silicon structures are left after the lateral expansion of the silicon structures during the oxidation [19] (Fig. 5b).…”