Fabrication of Ultrasmall Si Encapsulated in Silicon Dioxide and Silicon Nitride as Alternative to Impurity Doping

Abstract

The complementary metal oxide semiconductor (CMOS) technology is the foundation of our modern computers. Impurity doping is an essential technique for realizing CMOS devices, enabling many of their electronic key properties. [1] Hence, the type and density of impurity dopants is at the center of device design, allowing for the versatility and adaptability of CMOS technology to virtually every semiconductor technology, from analog design to verylarge-scale integration (VLSI). By scaling down CMOS transistor dimensions, the influence of the applied gate potential on the channel current decreased. This phenomenon, known as short channel effects, gave rise to the introduction of silicon-oninsulator (SOI) substrates, the development of field-effect transistors (Fin-FET) technology, and the upcoming gate-all-around (GAA)-FET technology. With increasing surface to volume ratio, impurity doping on the nanoscale faces the problems of dopant inactivation, due to increased ionization energy as a consequence of dielectric mismatch, [2,3] the dopant out-diffusion being on the same length scale as the gate length, [4,5] and statistical fluctuations of the dopant concentration in nanoscale volume transistors, [4,6,7] leading to unpredictable device behavior. The deactivation of dopants near the surface in nanowires effectively increases the resistance of GAA-FETs. Besides the aforementioned issues, dopants can freeze out at low temperatures, leaving them electronically inactive and restricting their application in cryoelectronics. With these drawbacks it would be beneficial to avoid impurity doping altogether, enabling further downscaling of transistors below the dopant out-diffusion limit of drain and source regions.Based on density functional theory (DFT) calculations, the effect of a nanoscale electronic structure shift induced by anions at surfaces (NESSIAS) was predicted [8,9] and would allow very steep p-n junctions on GAA-FETs with a diameter of a few nanometers. [10] Recently we demonstrated the NESSIAS effect on ultrathin Si-NWs as a function of Si thickness and embedding dielectric, with SiO 2 and Si 3 N 4 yielding effective n-and p-type doping, respectively. [10][11][12][13] The conduction band edge of these samples was measured with grazing incidence X-ray absorption spectroscopy in total fluorescence yield (XAS-TFY) and the

Toward Low‐Power Cryogenic Metal‐Oxide Semiconductor Field‐Effect Transistors

“…In order to study the NESSIAS effect experimentally, ultrathin single-crystalline silicon quantum wells were etched out of silicon-on-insulator substrates and wrapped in SiO 2 (for details, see refs. [38,40,43]); a transmission electron microscopy image of such a quantum well is shown in the inset of Figure 10. Subsequently, synchrotron X-ray absorption spectroscopy at total fluorescence (XAS-TFY) yield as well as ultraviolet photoemission spectroscopy (UPS) measurements were carried out at the BACH and BaDelPh beamlines in the study by Trieste.…”