Fabrication Technique for pMOSFET poly-Si/TaN/TiN/HfSiAlON Gate Stack

Abstract

Technique for the fabrication of a pMOSFET poly-Si/TaN/TiN/HfSiAlON gate stack is successfully developed. Direct deposition of poly-Si on the TiN metal gate suffers from a series of issues, such as large poly-Si grain size, bad poly-Si topography, visible voids and poor thermal stability. These issues can be solved by the introduction of TaN barrier layer between the poly-Si and TiN metal gate layers using a newly developed poly-Si deposition process. Then, the etch rate and profile of the TaN/TiN stack are systematically investigated with BCl3-based plasmas after the formation of poly-Si/TaN/TiN/HfSiAlON structure. A vertical profile of the TaN/TiN stack is finally obtained by utilizing the optimized BCl3/Cl2/O2/Ar plasma. Moreover, a high selectivity of HfSiAlON relative to the Si substrate is realized by utilizing the BCl3/Ar plasma combined with a DHF/HCl/alcohol solution strategy. Finally, good electrical characteristics further prove that the newly developed technique is a practicable process for pMOSFET device fabrication.