FAC-V: An FPGA-Based AES Coprocessor for RISC-V

Abstract

In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open RISC-V Instruction Set Architecture (ISA), the FPGA technology provides endless opportunities to create reconfigurable IoT devices with different accelerators and coprocessors tightly and loosely coupled with the processor. When connecting IoT devices to the Internet, secure communications and data exchange are major concerns. However, adding security features requires extra capabilities from the already resource-constrained IoT devices. This article presents the FAC-V coprocessor, which is an FPGA-based solution for an RISC-V processor that can be deployed following two different coupling styles. FAC-V implements in hardware the Advanced Encryption Standard (AES), one of the most widely used cryptographic algorithms in IoT low-end devices, at the cost of few FPGA resources. The conducted experiments demonstrate that FAC-V can achieve performance improvements of several orders of magnitude when compared to the software-only AES implementation; e.g., encrypting a message of 16 bytes with AES-256 can reach a performance gain of around 8000× with an energy consumption of 0.1 μJ.

Dynamic encryption method for MQTT communication

“…First, AES (Advanced Encryption Standard) is one of the most widely used symmetric encryption algorithms [8] . AES uses different key lengths (128,192, and 256 bits), and have high cryptographic strength after multiple rounds of displacement and substitution operations.…”

A novel reduced instruction set computer-communication processor design using field programmable gate array

“…The RISC processor is innovative in design to accommodate several applications in real-time. The fusion of the RISC processor with the advanced encryption standard (AES) cryptography algorithm is implemented in the FPGA to achieve high performance and reduction in delay [11], [12]. The FPGAimplemented RISC V processor is utilized for the comprehension of the design flow, hardware incorporation, communication protocols for computer engineers and fault analysis in single event transients [13]- [15].…”