Factors Affecting Copper Filling Process Within High Aspect Ratio Deep Vias for 3D Chip Stacking

Kim, B.; Sharbono, C.; Ritzdorf, T.; Schmauch, Dan

doi:10.1109/ectc.2006.1645755

Cited by 33 publications

(8 citation statements)

References 6 publications

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“…But here also, perfect filling without voids is required to avoid interconnect failures and/or later reliability issues. Several studies have already been undertaken [1][2][3][4][5][6][7][8] on how to achieve a voidfree plating of TSV, but more is needed to fully understand the role of additives and plating process parameters in the void-free fill of these challenging features.…”

Section: Amongmentioning

confidence: 99%

The Role of Additives and Deposition Parameters in Cu Plating of High Aspect Ratio Vias

Ko,

Radisic,

Armini

et al. 2009

Meet. Abstr.

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Section: Amongmentioning

confidence: 99%

The Role of Additives and Deposition Parameters in Cu Plating of High Aspect Ratio Vias

Ko,

Radisic,

Armini

et al. 2009

Meet. Abstr.

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“…However, most of those studied are focused on the via with the depth of less than 150 μm, while the actual demand of TSV with high depth (>200 μm) has become more and more urgent in 3D IC intergradation to decrease the wafer break risk after CMP thinning and improved the packing density. In the filling tests with various via dimensions, Kim et al found that it is more difficult to get defect-free filling of the deeper via [26]. In the study of the dynamic TSV filling process, Wang et al found that via with a depth of 60 μm and 100 μm can achieve defect-free filling by optimizing the plating parameters, while via with a depth of 200 μm cannot [27].…”

Section: Introductionmentioning

confidence: 99%

The key role of suppressor diffusion in defect-free filling of the through-silicon-via with high depth

Wang

Liu

2019

J. Micromech. Microeng.

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Defect-free filling of through-silicon-via (TSV) with high depth is still a challenge to obtain in the industry. Herein, physical quantities, i.e. deposited copper morphology, local current density, local coverage of additives and local concentrations of additives, were investigated in the filling process of TSV with high depth. It was found that the local current density was controlled by the local coverage of accelerator. And the competitive adsorption process of additives was dominated by the suppressor. Therefore, the limited diffusion of the suppressor gave rise to the pinch-off defect of the TSV with high depth. Moreover, ultrasonic vibration was used to promote the diffusion of the suppressor, and defect-free filling of the TSV with high depth was implemented.

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“…Three-dimensional (3D) electronic packaging is an essential way for microelectronic technology to move towards high density and large scale. The stack packaging technology based on through silicon via (TSV) vertical connection that represents one of the latest examples of scaling, has the capability of reducing the interconnect delay and realizing more complicated multichip system integration [3][4][5][6][7][8]. TSV is essentially a coated metal via residing in a silicon substrate for vertical interconnection.…”

Section: Introductionmentioning

confidence: 99%

A novel bottom–up copper filling of blind silicon vias in 3D electronic packaging

Shi

et al. 2015

J. Micromech. Microeng.

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Through silicon via is a promising technology that has benefits of high density, excellent performance and heterogeneous integration for 3D stacked devices, where blind silicon via plating in via first and via middle approaches is widely used. However, using conventional damascene copper plating technology to achieve high quality copper filling of blind vias is very difficult. In this paper, we demonstrate a novel approach for realizing bottom–up copper filling of blind silicon vias. Electroplating of the blind vias is carried out by using a titanium barrier layer, instead of the traditional copper seed layer, as the conductive medium. A vacuum process is introduced to push photoresist completely into the blind vias. By controlling the exposure and development processes, the photoresist at the top and middle of the vias is removed while that at the bottom it is retained for protecting the seed layer. After etching the exposed seed layer, we obtain a unique metal layer structure in which the copper seed layer is reserved at the via bottom, facilitating spontaneous bottom–up plating. Using this approach, we realize high quality copper filling of blind silicon vias of 30 µm in diameter and 120 µm in depth, which will be of noteworthy benefit in 3D electronic packaging.

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Factors Affecting Copper Filling Process Within High Aspect Ratio Deep Vias for 3D Chip Stacking

Cited by 33 publications

References 6 publications

The Role of Additives and Deposition Parameters in Cu Plating of High Aspect Ratio Vias

The Role of Additives and Deposition Parameters in Cu Plating of High Aspect Ratio Vias

The key role of suppressor diffusion in defect-free filling of the through-silicon-via with high depth

A novel bottom–up copper filling of blind silicon vias in 3D electronic packaging

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