Failure analyses of 3D Sip (system-in-package) and WLP (wafer-level package) by finite element methods

Abstract

In this study , three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the filled copper; (2) the failures of the micro bumps between the fine-pitch IC chip and the TSV interposer (chip) due to the global thermal expansion mismatch between the silicon IC Chip and the copper filled TSV interposer (chip); and (3) the failures of leadfree solder joints of a wafer-level chip scale package (WLCSP) due to the thermal expansion mismatch between the silicon WLCSP and the FR-4 epoxy printed circuit board (PCB). The results show that finite element method is not only able to identify the failure locations and determine the stress and strain to cause failures but also perform design for reliability.

Reliability approach of high density Through Silicon Via (TSV)

“…Thermo-mechanical finite element analysis often pointed on the TSV bottom corner as the critical region for reliability issues [2,8]. From this status, TCT and EM tests were performed to analyse whether this polymer film enhance failure.…”

Board level WLCSP 3D thermal stress analysis by submodeling of FEA

“…Fig.2. For the global thermal expansion mismatch between the chip, the solder joints and the PCB, the solder joint failure takes place at the chip corner under cyclical thermal loadings [7]. As the global model is hard to consider the very small structures, e.g.…”

Strain Gradient Finite Element Analysis of Size Dependence of Thermal Stresses in Through-Silicon Vias (TSVs)

“…The thermal stresses in TSV structures were simulated by many researchers by FEM [2][3][4][5]. Ranganathan et al [2] and Lau et al [4] concluded that the thermal stresses get worse with larger and deeper copper via structures.…”

“…The thermal stresses in TSV structures were simulated by many researchers by FEM [2][3][4][5]. Ranganathan et al [2] and Lau et al [4] concluded that the thermal stresses get worse with larger and deeper copper via structures. In the above simulations, SiO 2 and Si were assumed to be elastic and the Cu was assumed to be elastic-plastic.…”

“…In the above simulations, SiO 2 and Si were assumed to be elastic and the Cu was assumed to be elastic-plastic. The metal core materials have been found to exhibit a large plastic deformation in the corners of the TSV structure [2][3][4][5]. Nowadays, most system companies are pursuing smart electronic portable devices to answer the market demand for highly-miniaturized, high-performance and low-cost systems.…”