Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

Le, Fuliang; Lee, S. W. Ricky; Lo, Jeffery C. C.; Yang, Can

doi:10.1109/tcpmt.2015.2477075

Cited by 3 publications

(2 citation statements)

References 21 publications

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“…The underfill encapsulant was a commercial Loctite product. A jet valve was used to dispense free dots of the encapsulant into the central TSVs [21]. The central TSVs function as entrances for dispensing and an uninterrupted point-source to provide fluid for each layer.…”

Section: Underfill Dispensing Via Central Tsvmentioning

confidence: 99%

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3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Le¹,

Lee²,

Zhang³

2017

J. Micromech. Microeng.

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3D chip stacking with through silicon vias (TSVs) has been identified as one of the major technologies for achieving higher silicon packaging density and shorter interconnect. The test vehicle presented in this paper is a 3D chip stack package. Each layer of the test vehicle has two silicon flip chips mounted at the bottom of a silicon interposer with solder bumps. The flip chip has the equivalent dimensions and pad patterns as commercial memory chips. The interposer, with multiple interconnect TSVs for electrical connection and a central TSV for underfill dispensing, can function as a logic chip or as a redistribution chip in a real application. The assembly steps of the test vehicle include conductive adhesive filling for the interconnect TSVs, bonding two bumped flip chips on an interposer (to form a single layer), vertical stacking of the single layers and underfill dispensing. For the filling of the interconnect TSVs, an auger-dispensing method is first adopted to overfill the interconnect TSVs, followed by removing the excessive adhesive beyond the interconnect TSVs by squeegeeing. A jet valve continuously dispenses free dots of an underfill encapsulant into the central TSVs. The central TSVs function as an entrance for underfill dispensing and an uninterrupted point-source to provide fluid for each layer. The free dots form a capillary flow to fill the under-chip spaces of the test vehicle. The usage of TSVs rather than chip edges eliminates the presence of a wide edge reservoir, resulting in smaller ‘keep-out’ area occupation on the substrate.

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Section: Underfill Dispensing Via Central Tsvmentioning

confidence: 99%

“…The underfill flow between two adjacent chips (interposer or flip chip) can be considered as an incompressible, quasisteady, laminar and capillary flow [21,22]…”

Section: Underfill Dispensing Via Central Tsvmentioning

confidence: 99%

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Le¹,

Lee²,

Zhang³

2017

J. Micromech. Microeng.

Self Cite

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Characterization of Copper Diffusion in Through Silicon Vias

Zhang

Lee

2016

Materials for Advanced Packaging

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Effect of Sn/Cu thickness ratio on the transformation law of Cu₆Sn₅ to Cu₃Sn in Sn/Cu interface during aging

Zhang¹,

Sun²,

Guo³

2018

Mater. Res. Express

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Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

Cited by 3 publications

References 21 publications

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Characterization of Copper Diffusion in Through Silicon Vias

Effect of Sn/Cu thickness ratio on the transformation law of Cu₆Sn₅ to Cu₃Sn in Sn/Cu interface during aging

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Failure Analysis and Experimental Verification for Through-Silicon-via Underfill Dispensing on 3-D Chip Stack Package

Cited by 3 publications

References 21 publications

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

3D chip stacking with through silicon-vias (TSVs) for vertical interconnect and underfill dispensing

Characterization of Copper Diffusion in Through Silicon Vias

Effect of Sn/Cu thickness ratio on the transformation law of Cu6Sn5 to Cu3Sn in Sn/Cu interface during aging

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Product

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Effect of Sn/Cu thickness ratio on the transformation law of Cu₆Sn₅ to Cu₃Sn in Sn/Cu interface during aging