Failure detection and correction for clock ensemble in space

Zenzinger, A.; Bartusch, T.; Kuehl, C.; Fischer, Sylvain; Shrestha, Abhinandan

doi:10.1109/navitec.2012.6423054

Cited by 7 publications

(5 citation statements)

References 7 publications

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“…T. Anwar et al supported this finding by developing a built-in error correction for the same clock cycles in FPGA cells [57]. Two clock correction algorithms called a Kalman filter and weighted-average-based NIST AT1 were investigated by A. Zenzinger et al to detect failures and perform corrections from developed clock monitoring and a control unit [58]. This present work focused on automatic clock correction for an aging circuit, as shown in Figure 8.…”

Section: Proposed Automatic Clock Correctionmentioning

confidence: 74%

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

et al. 2021

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.

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Section: Proposed Automatic Clock Correctionmentioning

confidence: 74%

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

et al. 2021

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“…It is worth noting that we can derive an overall model test by approximating the gamma distribution (33) to a Gaussian distribution. This holds for a number of degrees of freedom p τ ,W sufficiently large, which occurs when the sampling interval τ is small compared to the window length W. Under this approximation we can follow the same procedure previously derived for tests on the phase measurements: compute the DAVAR residuals as the difference between observed and expected behaviors, and derive the null and alternative hypotheses, which would be in the same form of ( 19) and (25). However, in this paper we only focus on the w-test derived from the exact distribution (33) of ξ, which is valid for any sampling interval.…”

Section: Dynamic Allan Variancementioning

confidence: 94%

“…Other techniques for fault detection in clock signals include trend analysis and filtering of the frequency signal [18][19][20], the optimal stopping method [21], and interferometric analysis [22]. Fault detection in clock ensembles is further discussed in [23][24][25] using Kalman filters. Instead, the methods in [26][27][28] use least-squares fitting, standard deviation computed on sliding windows, and infinite impulse response filters.…”

Section: State Of the Artmentioning

confidence: 99%

Detection and identification of faults in clock ensembles with the generalized likelihood ratio test

2022

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In this paper we propose an approach for performing fault detection and identification in clock ensembles based on the generalized likelihood ratio test. We show that by applying a set of purposefully-designed statistical tests, one can successfully detect faults occurring in a clock of the ensemble, and identify which measurement in the ensemble is most likely to have triggered the detection. We first develop the theoretical framework for the characterization of the detectors and their performance, and validate the derivations via Monte Carlo simulations. Then, we apply the statistical tests to an ensemble of cesium clocks, aiming at detecting and identifying three types of non-nominal behaviors. The faulty conditions are obtained by injecting a pattern of phase steps, a phase and frequency drift, and an oscillatory phase component.

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“…Originally developed for atomic clocks, clock ensembling can be used for commercial off the shelf (COTS) oven-compensated oscillators too [20]. Although the approach of creating clock ensembles is well-established in theory and various simulation results exist (e.g., for atomic time keeping), there are few results with implementation in embedded devices and often demonstrations are limited to specialized contexts ( [26,27]), especially with low-cost oscillators.…”

Section: Related Workmentioning

confidence: 99%

High-precision Hardware Oscillators Ensemble for GNSS Attack Detection

Spanghero,

Papadimitratos

2022

Preprint

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A wide gamut of important applications rely on global navigation satellite systems (GNSS) for precise time and positioning. Attackers dictating the GNSS receiver position and time solution are a significant risk, especially due to the inherent vulnerability of GNSS systems. A first line of defense, for a large number of receivers, is to rely on additional information obtained through the rich connectivity of GNSS enabled platforms. Network time can be used for direct validation of the GNSS receiver time; but this depends on network availability. To allow attack detection even when there are prolonged network disconnections, we present a method based on on-board ensemble of reference clocks. This allows the receiver to detect sophisticated attacks affecting the GNSS time solution, independently of the specific attack methodology. Results obtained with Chip-Scale Oven Compensated Oscillators (CS-OCXO) are promising and demonstrate the potential of embedded ensembles of reference clocks, detecting attacks causing modifications of the receiver time offset as low as 0.3 µs, with half the detection latency compared to related literature.

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Failure detection and correction for clock ensemble in space

Cited by 7 publications

References 7 publications

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance

Detection and identification of faults in clock ensembles with the generalized likelihood ratio test

High-precision Hardware Oscillators Ensemble for GNSS Attack Detection

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