Failure mechanisms of boards in a thin wafer level chip scale package

Rajmane, Pavan; Khan, Hassaan Ahmad; Doiphode, Aniruddha; Rahangdale, Unique; Agonafer, Dereje; Lohia, Alok; Kummerl, Steven; Nguyen, Luu

doi:10.1109/itherm.2017.7992611

Cited by 10 publications

(1 citation statement)

References 6 publications

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“…Factors such as PCB thickness & copper density, solder alloy choice, type of organic laminate material, glass weave density, and mechanical hardware induced strain of the fi nished assembly can all affect the long-term solder joint reliability related to solder fatigue however any accelerated stress testing analysis performed without consistent solder joint quality will result in confounding data [7][8][9][10][11][12]. In order to better understand the variables that affect BTC package solder joint geometries a test vehicle was designed allowing for different variables to be tested.…”

Section: Experimental Setup Pcb Test Vehicle Configurationmentioning

confidence: 99%

Freeze Frame Reflow to Enhance Yields for Advanced Low-Profile Bottom Terminated Packages

Kummerl,

Sreenivasan,

Paku

et al. 2023

Journal of SMT

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Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more circuit board real estate toward end-user applications – all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. Unlike most gull wing style leaded packages, QFNs (Quad Flat Pack No lead packages) also known as BTCs (Bottom Terminated Components) have coplanar terminals below the package body to answer this ever-decreasing form-factor requirement. The final standoff in these QFN style packages are dictated by the solder joint geometry formed. Within this advanced package family also finding a similar trend are power WCSPs (Wafer Chip Scale Packages) where traditional solder spheres are being replaced with low profile interconnects in expanded and asymmetrical geometries. This paper presents factors that influence advanced low standoff package solderability performance with the use of video microscopy and live in situ X-ray reflow. To reflect the QFN board assemblies that are typically designed a series of layouts were implemented across different coupon test boards. Assembled coupon test board were designed by varying 1) through hole via design, 2) solder mask tenting techniques, 3) periphery and center thermal pad printed solder joint volumes, 4) no-clean and water-soluble solder paste flux chemistry all using SAC 305 alloy and type 4.5 powder size. One case study using live in-situ X-ray system will explain the effects of a QFN land pattern layout incorporating vias in the center thermal pad with solder mask tenting over the via openings located on the back of the PCB. In another configuration vias were removed from the center thermal pad and vacuum reflow performed during the liquidus phase of the solder with an explanation of why some of the voids remained. The first and second order results presented within this paper have practical implications and from their observations a novel process evaluation technique coined as Freeze Frame Reflow (FFR) was developed. In the last case study presented, an advanced mrQFN (multi-row QFN) package is investigated for factors affecting yields. FFR is then implemented resulting in an increase in yield further demonstrating the benefits this new & novel technique can offer.

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