False history filtering for reducing hardware overhead of FPGA-based LZ77 compressor

Choi, Sang Woong; Kim, Young-il; Song, Yong Ho

doi:10.1016/j.sysarc.2018.06.001

Cited by 5 publications

(10 citation statements)

References 4 publications

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“…Conversely, in compression-ratio-priority mode, more searches and comparisons are done to increase the compression ratio. They also implement ''false history filtering'' in their design (from a previous paper of theirs [15]) in which string-tags are also stored along with string-positions in the hash table. Before performing string comparisons, the tags are checked to see if the strings are remotely similar or were two very different strings that happened to hash to the same signature.…”

Section: Literature Review a Compression-related Workmentioning

confidence: 99%

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

2020

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The Deflate compression algorithm provides one of the most widely used solutions for lossless data compression. Field-programmable gate arrays (FPGAs) are commonly used to implement hardware accelerators that speed up computation-intensive applications. In this article, FPGA-based accelerators for Deflate compression and decompression are described. These accelerators were specified in C++ and synthesized using Vivado High-Level Synthesis (HLS) for a Xilinx Virtex UltraScale+ series FPGA and a system clock frequency of 250 MHz. The proposed compressor processes data at a fixed input throughput of 4.0 GB/s and achieves a geometric mean compression ratio of 1.92 on the Calgary corpus benchmark files using static Huffman encoding. While not the first compressor synthesized using high-level synthesis, our design achieves a 25% greater throughput and an 11% greater compression ratio than the only other published design that uses Vivado HLS. The proposed decompressor design achieves average input throughputs of 196.61 MB/s and 97.40 MB/s, for statically and dynamically encoded Calgary corpus files, respectively. This is the first published decompressor design that is synthesized using high-level synthesis and provides performance that is comparable to that of the best published designs, having static throughputs 11% higher and dynamic throughputs only 10% lower than the expertly-optimized design sold by Xilinx.

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Section: Literature Review a Compression-related Workmentioning

confidence: 99%

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

2020

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“…False history filtering is a technique to detect unnecessary comparison operations that occur during the LZ77 operation [24]. To determine whether histories from the hash table affect CR, this technique stores a portion of the three-byte string (filtering tag) used for the hash key with history.…”

Section: Reducing Comparison Process With False History Filteringmentioning

confidence: 99%

“…In this section, we describe the proposed LZ77 acceleration architecture. We designed the accelerator based on the prototype of the LZ77 acceleration hardware proposed in the previous study [24]. Unlike the previous structure that searches only one string per unit operation, the proposed architecture selects multiple target strings per one unit operation to improve the performance.…”

Section: Architecture Overviewmentioning

confidence: 99%

“…The proposed accelerator determines the degree of parallelism of the comparison operation dynamically. To determine the degree of parallelism during compression, the proposed architecture uses a comparison validity determination technique [24] to determine the level of parallelism that does not affect the CR. The necessity of additional adjustment of the degree of parallelism is determined according to the current operation mode of the compression accelerator and whether the necessary comparison operation can be performed in parallel within one cycle.…”

Section: Introductionmentioning

confidence: 99%

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Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput

et al. 2019

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Data compression reduces the cost of data storage and transmission by decreasing the data size. Previous studies have improved system performance by adaptively choosing the compression ratio (CR) and throughput required for the system by using a trade-off between them in the compression algorithm. Hardware accelerators are widely used to reduce the CPU load caused by compression operations. Several existing compression accelerators have low flexibility in changing the CR and bandwidth. This study proposes a hardware compression accelerator that can adjust the CR and throughput at runtime. The proposed architecture accelerates the LZ77 compression algorithm and supports the throughput-first (TF) and compression ratio-first (CF) modes by changing the degree of parallelism of comparison operations performed during the compression process. In addition, we propose a technique to dynamically change the degree of parallelism of the comparison operation to achieve a better throughput in CF mode and a better CR in TF mode. Experimental results demonstrate that the TF mode provides a throughput higher by 11.39%, and a CR lower by 0.07 than the CF mode. The value 0.07 accounts for 13.21% of the variation in the CR provided by the software implementation of LZ77.INDEX TERMS Accelerator architectures, data compression, field programmable gate arrays.

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“…For this reason, there have been many attempts to reduce the computational load of data compression by utilizing customized hardware resources, such as field-programmable gate arrays (FPGAs) [34]- [41], graphics processing units, and application-specific integrated circuits [42], [43]. These methods decrease the computational load on the processor by offloading a portion of the computations from the processor to a hardware offloading engine.…”

Section: Introductionmentioning

confidence: 99%

Low-Overhead Compressibility Prediction for High-Performance Lossless Data Compression

et al. 2020

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As big data has evolved over the past few years, a lack of storage space and I/O bandwidth has become one of the most important challenges to overcome. To mitigate these problems, data compression schemes reduce the amount of data to be stored and transmitted at the cost of additional CPU overhead. Many researchers have attempted to reduce the computational load imposed on the CPU by data compression using specialized hardware. However, space savings through data compression often comes from only a small portion of data. Therefore, compressing all data, regardless of data compressibility, can waste computational resources. Our work aims to decrease the cost of data compression by introducing a selective data compression scheme based on data compressibility prediction. The proposed compressibility prediction method provides more fine-grained selectivity for combinational compression. Additionally, our method reduces the amount of resources consumed by the compressibility predictor, enabling selective compression at a low cost. To verify the proposed scheme, we implemented a DEFLATE compression system on a field-programmable gate array platform. Experimental results demonstrate that the proposed scheme improves compression throughput by 34.15% with a negligible decrease in compression ratio. INDEX TERMS Data compression, Huffman coding, LZ77 encoding, accelerator architecture, field programmable gate array, estimation, compressibility.

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False history filtering for reducing hardware overhead of FPGA-based LZ77 compressor

Cited by 5 publications

References 4 publications

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

Design of FPGA-Based LZ77 Compressor With Runtime Configurable Compression Ratio and Throughput

Low-Overhead Compressibility Prediction for High-Performance Lossless Data Compression

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