Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

Chen, Tung-Chien; Chen, Yuhan; Tsai, Sung-Fang; Chien, Shao-Yi; Chen, Liang-Gee

doi:10.1109/tcsvt.2007.894044

Cited by 87 publications

(39 citation statements)

References 20 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…One scenario is to show the data bandwidth savings without data bandwidth constraint. In this scenario, we use the search range to represent BW Bus for simplicity and compare with the full search with Level C data reuse scheme since it can achieve the highest data reuse [13], [25], [26]. Another scenario is to demonstrate the rate distortion performance under the data bandwidth constraint.…”

Section: B Proposed Bandwidth Aware Me Algorithmmentioning

confidence: 99%

RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access

Chang

2010

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

Abstract-Data bandwidth dominates the performance and power consumption in the video encoder design. In which a low bandwidth and bandwidth aware motion estimation design enables smooth and better video quality as well as lower power consumption on data accesses. This paper proposes a bandwidth efficient motion estimation and its hardware implementation to deal with the bandwidth issues. First, an on-demand data access mechanism is proposed to acquire the reference data according to the video content for motion estimation process and thus can avoid unnecessary reference data loading. Furthermore, the available bandwidth constraint is properly modeled into our proposed rate distortion optimization framework to efficiently use the data bandwidth. Simulation results show that our proposed algorithm not only allocates proper data bandwidth for motion estimation according to video content but also saves 79.15% data bandwidth demand with 0.03 dB PSNR drop and 2.50% bitrate increase in maximum for 4 CIF resolution sequences, when compared to the fully data reuse full search motion estimation which reuses the overlapped reference data to avoid unnecessary data reloading. In addition, under the available data bandwidth constraint, our proposed algorithm can achieve 2.43%, 0.08%, and 0.20% BD-bitrate saving with 0.17 dB, 0.01 dB, and 0.01 dB BD-PSNR increase on average for high, median, and low motion sequences when compared to the full search motion estimation algorithm. The resulted design only needs 75.27 K gate counts when running at 23 MHz operating frequency for 4 CIF at 30 frames/s with 90 nm CMOS process due to its search range independent buffer design.

show abstract

Section: B Proposed Bandwidth Aware Me Algorithmmentioning

confidence: 99%

RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access

Chang

2010

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

show abstract

“…Then, a content-aware algorithm is proposed to achieve good tradeoff between coding performance and computation complexity [13]. Finally, a parallel architecture and a memory organization technique are designed to support the proposed algorithm effectively [14].…”

Section: Integer Motion Estimationmentioning

confidence: 99%

Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices

Chen

Tsai

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

Abstract-Because video services are becoming popular on portable devices, power becomes the primary design issue for video coders nowadays. H.264/AVC is an emerging video coding standard which can provide outstanding coding performance and thus is suitable for mobile applications. In this paper, we target a power-efficient H.264/AVC encoder. The main power consumption in an H.264/AVC encoding system is induced by data access of motion estimation (ME). At first, we propose hardware-oriented algorithms and corresponding parallel architectures of integer ME (IME) and fractional ME (FME) to achieve memory access power reduction. Then, a parameterized encoding system and flexible system architecture are proposed to provide power scalability and hardware efficiency, respectively. Finally, our design is implemented under TSMC 0.18 µ µ µm CMOS technology with 12.84 mm 2 core area. The required hardware resources are 452.8 K logic gates and 16.95 KB SRAMs. The power consumption ranges from 67.2 to 43.5 mW under D1 (720 × 480) 30 frames/s video encoding, and more than 128 operating configurations are provided.

show abstract

“…In this paper, we proposed a low power cache algorithm for H.264/AVC fast ME based on our previous works [2,7]. The previous hardware-oriented content-adaptive four-step search and data reuse strategy had successfully minimized the power of ME logic and SR memory reading.…”

Section: Proposed Algorithmmentioning

confidence: 99%

Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Tsai

Chung

Chen

et al. 2007

2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07

Self Cite

View full text Add to dashboard Cite

Low power Motion Estimation (ME) of H.264/AVC is an important research issue because of the growing mobile applications of H.264/AVC encoder. In this paper, low power cache algorithm and architecture for fast ME of H.264/AVC is proposed in order to replace the conventional Search Range (SR) memory. With the Block Translation (BT) cache architecture, Search Trajectory Prediction (STP) prefetching algorithm, and ultra low power Cache Miss Hiding (CMH) strategy, 35% SR memory writing power and 67% SR memory static power are reduced for DI videos. Combining fast ME with the proposed cache provides the total solution for low power ME hardware.

show abstract

Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC

Cited by 87 publications

References 20 publications

RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access

RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access

Algorithm and Architecture Design of Power-Oriented H.264/AVC Baseline Profile Encoder for Portable Devices

Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Contact Info

Product

Resources

About