Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Tsai, Chuan-Yuan; Chung, Chen-Han; Chen, Yuhan; Chen, Tung-Chien; Chen, Liang-Gee

doi:10.1109/icassp.2007.366181

Cited by 15 publications

(12 citation statements)

References 7 publications

(3 reference statements)

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“…Previous work shows that the SR utilization is only 30% on CIF video, and it decreases to 15% on D1 video [7]. That is to say, many data read to the SR buffer are never used.…”

Section: Problem Statementmentioning

confidence: 97%

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Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

Chen

Ding

Tsung

et al. 2008

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

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High Definition (HD) video compression enables vivid reproduction of scenes. However, Motion Estimation (ME) requires large memory capacity and huge memory bandwidth, which are undesirable in many platforms including ASIC and SoC. In this paper, an algorithm and architecture design of cache system and fast ME in HD H.264/AVC are proposed. With the proposed cache system and hardware-oriented fast ME algorithm, the rate-distortion performance is maintained within 0.03dB difference, the size of on-chip memory reduced to only 10% to 21% of original size, while the external memory bandwidth from cache refill is also 18% to 56% less than that of level C data reuse scheme with vertical 64 search range.

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“…Previous work shows that the SR utilization is only 30% on CIF video, and it decreases to 15% on D1 video [7]. That is to say, many data read to the SR buffer are never used.…”

Section: Problem Statementmentioning

confidence: 97%

“…From the work in [7], if we want a reasonable RD performance, cache size is 1/3 of level C buffer size for D1 video, and the ratio is 2/3 for CIF video. From this trend, we can expect the ratio be smaller on HD video.…”

Section: Problem Statementmentioning

confidence: 99%

Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

Chen

Ding

Tsung

et al. 2008

2008 IEEE International Conference on Acoustics, Speech and Signal Processing

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“…The ME/DE of an MB is predicted as the average of the ME/DE processing time of all the matching neighbors in the 3D-neighborhood. Afterwards, the leakage savings are compared with the wakeup energy overhead and the sectors are set in their respective power modes (lines [14][15][16][17]. In case of P OFF , additionally E MissGroup is considered as P OFF results in the loss of data in memory sectors and require a re-fetching (line 16).…”

Section: B Video Content-driven Power Managementmentioning

confidence: 99%

“…Furthermore, not all parts of the search window stored in the on-chip memory are accessed because of the adaptive nature of fast ME/DE algorithms (like TZ Search [5]) and diverse texture/motion properties of MBs (see memory usage analysis in Section II.A). To address this issue, the work of [14] employs adaptive window sizing. However, this work targets a fixed Four-Step Search and does not account for DE and leakage power, which is a crucial power component.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Adaptive power management of on-chip video memory for multiview video coding

Shafique,

Zatt,

Walter

et al. 2012

Proceedings of the 49th Annual Design Automation Conference

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An adaptive power management of on-chip video memory for Multiview Video Coding is presented. It leverages texture, motion and disparity properties of objects and their correlations in the 3D-neighborhood. It groups different Macroblocks of a frame and predicts the highly-probable motion/disparity search direction in order to power-gate idle memory regions. Exploited are the statistical properties of Macroblock groups to predict idle sectors. Our approach achieves on average 32% and 61% energy reduction (averaged over various video sequences) compared to state-of-the-art DSW [7] and Level C [12], respectively. The Motion/Disparity Estimation architecture with video memory and power management scheme is implemented using an ASIC flow (IBM-65nm Low-Power technology) and it processes 4-view HD1080p@33fps.

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“…However, their results are for CIF/QCIF videos which require a small search space for block-matching. In [21], the on-chip memory is replaced with a cache. Further, the leakage energy reduction is not considered.…”

Section: Related Workmentioning

confidence: 99%

AMBER: Adaptive energy management for on-chip hybrid video memories

Khan

Shafique

Henkel

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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The ever increasing leakage power of memories in a system has motivated researches for exploiting unconventional memory architectures. Non-Volatile Memory (NVM) used in conjunction with the conventional on-chip SRAMs has given birth to the hybrid memory paradigm, which can be intelligently exploited to reduce the energy consumption while tackling the high read and write latencies of NVMs. We present a novel scheme AMBER that aims at minimizing the total memory energy consumption of a video processing system by leveraging the application-specific properties and distinct latency and power properties of different memory types. AMBER also features architectural support for data-fetching from external memory and adaptively filling the different on-chip memories. We employ AMBER in the next-generation High Efficiency Video Coding (HEVC) standard to minimize the energy consumption of the new complex motion prediction process. Experimental results demonstrate that our AMBER scheme achieves significant energy savings (average 43%) for the on-chip memory.

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Low Power Cache Algorithm and Architecture Design for Fast Motion Estimation in H.264/AVC Encoder System

Cited by 15 publications

References 7 publications

Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

Algorithm and architecture design of cache system for motion estimation in high definition H.264/AVC

Adaptive power management of on-chip video memory for multiview video coding

AMBER: Adaptive energy management for on-chip hybrid video memories

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