Fast Algorithm and Low-Cost Hardware-Sharing Design of Multiple Integer Transforms for VC-1

Abstract

In this brief, the fast 1-D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1-D integer transforms are hardware shared, and they can be applied to the 2-D transform scheme. The hardware costs of the proposed fast 1-D and 2-D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec

Cost-effective multi-standard video transform core using time-sharing architecture

“…The MPEG, H.264, VC-1, and HEVC standards use the same 8-point coefficient structure; therefore, the 8-point transform used for these standards can be obtained via the same mathematical derivation. The symmetry of the IDCT coefficient makes it possible for the 1-D 8-point IDCT in (1) to be expressed as (4) and divided into an even part z e and an odd part z o , as listed in (5) and (6), respectively:…”

“…Numerous transform architectures supporting single standards have been developed to reduce hardware costs [5][6][7]. The architecture for the Video Codec 1 (VC-1) standard uses matrix decomposition, additions, and row/column permutations to reduce hardware costs [5].…”

“…Numerous transform architectures supporting single standards have been developed to reduce hardware costs [5][6][7]. The architecture for the Video Codec 1 (VC-1) standard uses matrix decomposition, additions, and row/column permutations to reduce hardware costs [5]. The two-dimensional (2-D) forward and inverse discrete cosine transform (DCT and IDCT) use a single 1-D transform core and a transpose memory with time division to enhance area-efficiency and achieve highthroughput rates for the MPEG standard [6].…”

“…This architecture uses an efficient constant matrix multiplication scheme implemented in HEVC for DCT. As outlined in [5][6][7], high area-efficiency and high-throughput rates can be achieved using these architectures to support single standard; however, this approach is unable to match various transforms supporting different standards that designed to support a single standard.…”