Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Azarpeyvand, Ali; Salehi, Mostafa E.; Fakhraie, S.M.; Safari, Saeed

doi:10.1016/j.micpro.2016.01.012

Cited by 8 publications

(4 citation statements)

References 16 publications

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“…Existing studies [7], [8] have introduced metrics to help evaluate the impact of errors by formulating vulnerability metrics, such as the application vulnerability factor (AVF). However, such metrics rely on exhaustive error-injection campaigns that use single bit-flip models.…”

Section: Error Modelling and Error Vulnerability Estimationmentioning

confidence: 99%

“…Nevertheless, these models have neglected some important microarchitecture features and were not used to estimate the susceptibility of any code to timing errors early at the design cycle to help designers choose appropriate design options. Only few existing studies tried to estimate the vulnerability of applications to errors by evaluating different metrics [7], [8]. Typically, such metrics are leveraged to evaluate either the impact of errors on applications or their reliability.…”

Section: Introductionmentioning

confidence: 99%

“…• We quantify the degree to which various applications are prone to timing errors by introducing a new significance-aware code vulnerability factor (SCVF). Unlike existing vulnerability metrics that rely on exhaustive error-injection campaigns and consider only the total number of manifested errors [7], [8], SCVF utilizes a ML-based error prediction model which is able to consider the exact time (i.e., instruction) and location (i.e., bit) of a timing error. This allows us to capture the significance of those errors to the output quality, without relying on long simulations.…”

Section: Introductionmentioning

confidence: 99%

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Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

et al. 2023

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The adoption of aggressively down-scaled voltages along with worsening process variations render nanometer devices prone to timing errors that threaten system functionality and output quality. In this paper, we introduce a significance-aware code vulnerability factor (SCVF) for early evaluation of the impact of such errors on applications. To estimate this metric, we propose the utilization of a microarchitecture-aware ML model for timing error prediction that jointly considers many instruction types, as well as all in-flight instructions in a pipeline. Finally, we validate the efficacy of SCVF by analyzing the output quality loss of various applications.

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Section: Error Modelling and Error Vulnerability Estimationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

et al. 2023

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“…Azarpeyvand et al [19] introduce the metric instruction vulnerability factor to quantify software vulnerability (extending the PVF metric) by also considering the microarchitecture details of the processor. In this, a custom fault-injection framework is used to analyze the impact of transient faults on the instruction set.…”

Section: B Related Workmentioning

confidence: 99%

Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability

Jeyapaul

Flores²,

Ávila

et al. 2017

IEEE Trans. VLSI Syst.

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Decades of rapid aggressive technology scaling have brought the challenge of soft errors to modern computing systems. Sequential elements (registers) in the processor pipeline exposed to charge-carrying particles generate bit flips or soft errors that could translate into system failures. Next to the processor cache, the pipeline registers (PRs)-registers between two pipeline stages-account for more than 50% of soft-error failures in the system. In this paper, for the first time, we apply architectural correct execution models that quantitatively define the vulnerability (or exposure to soft errors) of microarchitectural components, and extend it to define the vulnerability of PRs-PR vulnerability (PRV). We develop gemV-Pipe, a simulation toolset for the systematic, accurate, and quantitative estimation and analysis of PRV. Our detailed ISA-aware analysis in gemV-Pipe reveals interesting facts on the data-access behavior of PRs: 1) the vulnerability of each PR is not proportional to their size; 2) the PR bits used for one instruction may not be used (and are thus not vulnerable) for another, which makes PRV extremely instruction-dependent; and 3) the functionality of stored data on the PR bits can be used to classify them as-instruction, control, and data bits-each of which differ in their instructionspecific behavior and vulnerability. Applying the insight gained, we perform design space exploration on selectively hardening the PR bits, and demonstrate that 75% improved reliability can be achieved for only <15% power overhead.

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An automated framework for selectively tolerating SDC errors based on rigorous instruction-level vulnerability assessment

Ahmad,

Sedaghat

2024

Future Generation Computer Systems

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Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Cited by 8 publications

References 16 publications

Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

Estimating Code Vulnerability to Timing Errors Via Microarchitecture-Aware Machine Learning

Systematic Methodology for the Quantitative Analysis of Pipeline-Register Reliability

An automated framework for selectively tolerating SDC errors based on rigorous instruction-level vulnerability assessment

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